SIPO register with timing diagram

A serial-in parallel-out (SIPO) shift register takes data serially, one bit per clock, and makes all stored bits available at the same time on separate output lines. A 4-bit SIPO register is four cascaded D flip-flops with a common clock and an output taken from every flip-flop. The example below uses the data 1010.

Circuit

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Each flip-flop's Q drives the next D input, and all four Q outputs are brought out. At every clock edge: $QA \leftarrow D_{in},\ QB \leftarrow QA,\ QC \leftarrow QB,\ QD \leftarrow QC$.

Operation with data 1010

The register is first cleared (0000). The data is applied LSB first, so the serial input is 0, 1, 0, 1 at clocks 1 to 4.

• Storing: after the 4th clock, QA QB QC QD = 1010, which is 1010 with QA as MSB.
• Retrieving: the four outputs are read at once (in parallel) right after clock 4, so loading takes 4 clocks but reading takes no extra clock. (If clocking continues with input 0, the data shifts out at QD and the register clears after clock 8.)

Timing diagram

       1   2   3   4   5   6   7   8
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Din   ___|‾‾‾|___|‾‾‾|________________
QA    _____|‾‾‾|___|‾‾‾|______________
QB    _________|‾‾‾|___|‾‾‾|__________
QC    _____________|‾‾‾|___|‾‾‾|______
QD    _________________|‾‾‾|___|‾‾‾|__

SIPO registers are used for serial-to-parallel conversion, e.g. in a UART receiver.