Shift register and 4-bit PISO operation

Shift register

A shift register is a group of flip-flops connected in a chain, with a common clock, that stores a binary word and moves (shifts) it one bit position to the right or left at each clock pulse. An n-bit shift register has n flip-flops. Depending on how data is entered and taken out, there are SISO, SIPO, PISO, PIPO and bidirectional/universal shift registers. They are used for data storage, serial-parallel conversion, time delay, and ring/Johnson counters.

4-bit PISO shift register

The PISO register loads 4 bits in parallel in one clock and sends them out serially, one bit per clock. The example data is 1011.

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1011

Parallel inputs: PA PB PC PD = 1 0 1 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1011. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 1, 0, 1, i.e. 1011 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _____|‾‾‾|__________
QC      _|‾‾‾|___|‾‾‾|______
QD      _|‾‾‾‾‾‾‾|___|‾‾‾|__