PISO register with 1101 data

A PISO (parallel-in serial-out) shift register accepts all bits of a word at once and shifts them out one bit per clock. It is built from four D flip-flops; a control line SHIFT/LOAD' selects, through AND-OR gates, whether each flip-flop takes its parallel input bit (load) or the output of the flip-flop on its left (shift).

Circuit

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

 One stage (e.g. stage B):
 QA ---------->+-----+
 SH/LD' --+--->| AND |--+
          |    +-----+  |  +----+
          |             +->| OR |--> DB
          |    +-----+  +->|    |
          +NOT>| AND |--+  +----+
 PB ---------->+-----+
 DB = SH.QA + SH'.PB

• SH/LD' = 0 (load): the lower AND gates are enabled, so $D_A = P_A,\ D_B = P_B,\ D_C = P_C,\ D_D = P_D$. At one clock edge all four bits are stored at the same time.
• SH/LD' = 1 (shift): the upper AND gates are enabled, so $D_B = Q_A,\ D_C = Q_B,\ D_D = Q_C$ (and $D_A = 0$). Each clock moves the data one place right and the next bit appears at the serial output QD.

Storing and retrieving 1101

Parallel inputs: PA PB PC PD = 1 1 0 1 (PA = MSB, PD = LSB).

1. Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1101. The LSB (1) is already at the output QD.
2. Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 0, 1, 1 in turn.
3. Serial output after clocks 1 to 4: 1, 0, 1, 1, i.e. 1101 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.

Timing diagram

         1   2   3   4   5
CLK     _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD'  ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA      _|‾‾‾|______________
QB      _|‾‾‾‾‾‾‾|__________
QC      _____|‾‾‾‾‾‾‾|______
QD      _|‾‾‾|___|‾‾‾‾‾‾‾|__