- 2079 Bhadra · 6 marks
PISO register with 1010 data
Short answer
A 4-bit PISO register loads parallel data 1010 with SH/LD'=0, then shifts bits out LSB first with SH/LD'=1. The serial output sequence is 0,1,0,1 over four clocks. The timing diagram shows the load control and the resulting QD waveform.
Explain the working function of PISO register with timing diagram of 1010 data input.
A PISO register takes a word in parallel (all bits together) and gives it out serially (one bit per clock). The 4-bit version uses four D flip-flops with a SHIFT/LOAD' control and an AND-OR selector at each D input.
Circuit
PA PB PC PD
| | | |
+-----+ +-----+ +-----+ +-----+
0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
+-----+ | +-----+ | +-----+ | +-----+
| | | | | | |
+-----+ | +-----+ | +-----+ | +-----+
|D QA|-+ |D QB|-+ |D QC|-+ |D QD|-->
|> | |> | |> | |> | Serial
+-----+ +-----+ +-----+ +-----+ out
MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
SH/LD' and CLK are common to all stages.
One stage (e.g. stage B):
QA ---------->+-----+
SH/LD' --+--->| AND |--+
| +-----+ | +----+
| +->| OR |--> DB
| +-----+ +->| |
+NOT>| AND |--+ +----+
PB ---------->+-----+
DB = SH.QA + SH'.PB
- SH/LD' = 0 (load): the lower AND gates are enabled, so . At one clock edge all four bits are stored at the same time.
- SH/LD' = 1 (shift): the upper AND gates are enabled, so (and ). Each clock moves the data one place right and the next bit appears at the serial output QD.
Storing and retrieving 1010
Parallel inputs: PA PB PC PD = 1 0 1 0 (PA = MSB, PD = LSB).
- Store (clock 1, SH/LD' = 0): all bits load together: QA QB QC QD = 1010. The LSB (0) is already at the output QD.
- Retrieve (clocks 2, 3, 4, SH/LD' = 1): each clock shifts right and a 0 enters QA. QD shows 1, 0, 1 in turn.
- Serial output after clocks 1 to 4: 0, 1, 0, 1, i.e. 1010 read LSB first. One clock loads, and n - 1 = 3 more clocks deliver the remaining bits.
| CLK | SH/LD' | QA | QB | QC | QD | Serial out |
|---|---|---|---|---|---|---|
| 0 (initial) | - | 0 | 0 | 0 | 0 | - |
| 1 | Load | 1 | 0 | 1 | 0 | 0 |
| 2 | Shift | 0 | 1 | 0 | 1 | 1 |
| 3 | Shift | 0 | 0 | 1 | 0 | 0 |
| 4 | Shift | 0 | 0 | 0 | 1 | 1 |
| 5 | Shift | 0 | 0 | 0 | 0 | 0 |
Timing diagram
1 2 3 4 5
CLK _|‾|_|‾|_|‾|_|‾|_|‾|
SH/LD' ___|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
QA _|‾‾‾|______________
QB _____|‾‾‾|__________
QC _|‾‾‾|___|‾‾‾|______
QD _____|‾‾‾|___|‾‾‾|__
✓ Answer checked by Claude Opus 5.5 (high effort)
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