What are the machine cycles of LDA 2080H and the total T-states?

Opcode fetch, memory read, memory read, memory read: 13 T-states

Opcode fetch, memory read, memory write: 10 T-states

Opcode fetch, memory read, memory read: 10 T-states

Opcode fetch, memory read, memory read, memory read: 16 T-states

With a 6 MHz crystal, what is the time to execute LDA 2080H?

13 x 0.333 microsecond = 4.33 microseconds

13 x 0.167 microsecond = 2.17 microseconds

10 x 0.333 microsecond = 3.33 microseconds

13 x 0.5 microsecond = 6.5 microseconds

During M4 of LDA 2080H, which address is placed on the bus?

2080H, formed from W (20H) and Z (80H) read in M3 and M2

2003H, the next value of the program counter

2002H, the location of the high address byte

8020H, because the low byte is read first

Why is ALE high in T1 of every machine cycle in the timing diagram?

To mark that AD0-AD7 carries the low byte of the address, so it can be latched

To tell memory that a write operation will follow

To decode the opcode in the instruction register

To put the AD0-AD7 bus into high impedance

Asked 2/14
2071 Magh · 6+2 marks

Timing diagram of LDA 2080H

Short answer

LDA 2080H takes 13 T-states (opcode fetch, two reads for address, data read). Crystal 6 MHz gives internal clock 3 MHz, T=0.333 µs. Execution time = 13×0.333 = 4.33 µs.

Draw timing diagram of instruction LDA 2080H. Calculate the time required to execute this instruction if the crystal frequency is 6 MHZ.

LDA 2080H (opcode 3AH) loads A from memory location 2080H. It is a 3-byte instruction with 4 machine cycles: opcode fetch (4T), memory read (3T), memory read (3T), memory read (3T) = 13 T-states. Assume it is stored at 2000H, 2001H, 2002H as 3AH, 80H, 20H.

M-cycle	T	A15-A8	AD7-AD0	ALE	Control	IO/M S1 S0
M1 (opcode fetch, 4T)	T1	20H	00H (PCL)	1	-	0 1 1
	T2	20H	Hi-Z (bus floats)	0	RD low	0 1 1
	T3	20H	3AH (opcode in)	0	RD low, rises at end	0 1 1
	T4	-	-	0	none (decode)	0 1 1
M2 (memory read, 3T)	T1	20H	01H	1	-	0 1 0
	T2	20H	Hi-Z (bus floats)	0	RD low	0 1 0
	T3	20H	80H (data in)	0	RD low, rises at end	0 1 0
M3 (memory read, 3T)	T1	20H	02H	1	-	0 1 0
	T2	20H	Hi-Z (bus floats)	0	RD low	0 1 0
	T3	20H	20H (data in)	0	RD low, rises at end	0 1 0
M4 (memory read, 3T)	T1	20H	80H	1	-	0 1 0
	T2	20H	Hi-Z (bus floats)	0	RD low	0 1 0
	T3	20H	data (data in)	0	RD low, rises at end	0 1 0

      |  M1 (OF)  | M2 (MR) | M3 (MR) | M4 (MR) |
      |T1 T2 T3 T4|T1 T2 T3 |T1 T2 T3 |T1 T2 T3 |
 ALE  |HI lo lo lo|HI lo lo |HI lo lo |HI lo lo |
 RD   |hi LO LO hi|hi LO LO |hi LO LO |hi LO LO |
 WR   |hi hi hi hi|hi hi hi |hi hi hi |hi hi hi |

Explanation

M1: address 2000H (PC) is output, ALE high in T1; RD low in T2-T3; opcode 3AH enters IR, decoded in T4.
M2: address 2001H; the byte 80H (low address) is read into Z.
M3: address 2002H; the byte 20H (high address) is read into W.
M4: address WZ = 2080H is output; RD low; the data byte at 2080H is read into the accumulator.

Time

Crystal frequency = 6 MHz. The 8085 divides the crystal frequency by 2 internally, so the operating clock = 3 MHz.

T = 1 / 3 MHz = 0.333 microsecond

Time = 13 x 0.333 = 4.33 microseconds.

✓ Answer checked by Claude Opus 5.5 (high effort)

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Timing diagram of LDA 2080H

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