LDA C030H is stored at C050H. What does the CPU read in M2, from C051H?

30H, the low-order address byte, into the Z register

C0H, the high-order address byte, into the W register

The data byte at C030H, into the accumulator

The opcode 3AH, into the instruction register

During M4 of LDA C030H (stored at C050H), which address does the CPU put on the address bus?

C030H, taken from the W and Z registers

C052H, the last byte of the instruction

C050H, the address of the opcode

Asked 2/14
2070 Bhadra · 3 marks
2069 Poush · 3 marks

Machine cycles involved in LDA

Short answer

LDA C030H has four machine cycles and 13 T-states: opcode fetch at C050H, then memory reads at C051H, C052H, and C030H to get low address, high address, and data. The accumulator gets the byte from C030H and PC becomes C053H.

Write the various machine cycles involved in LDA C030 stored at C050. (Similar: various machine cycles involved in LDA 8050H instruction stored at memory location 8020H.)

LDA C030H (opcode 3AH) loads the accumulator with the byte at address C030H. It is a 3-byte instruction stored at C050H (3AH), C051H (30H), C052H (C0H). It has four machine cycles and 13 T-states.

Machine cycle	Type	Address	Operation	T-states
M1	Opcode fetch	C050H	Read opcode 3AH into IR, decode	4
M2	Memory read	C051H	Read low-order address byte 30H into Z	3
M3	Memory read	C052H	Read high-order address byte C0H into W	3
M4	Memory read	C030H (WZ)	Read data from C030H into A	3

Total = 4 + 3 + 3 + 3 = 13 T-states. PC = C053H after the instruction.

Bus status for each cycle:

M-cycle	T	A15-A8	AD7-AD0	ALE	Control	IO/M S1 S0
M1 (opcode fetch, 4T)	T1	C0H	50H (PCL)	1	-	0 1 1
	T2	C0H	Hi-Z (bus floats)	0	RD low	0 1 1
	T3	C0H	3AH (opcode in)	0	RD low, rises at end	0 1 1
	T4	-	-	0	none (decode)	0 1 1
M2 (memory read, 3T)	T1	C0H	51H	1	-	0 1 0
	T2	C0H	Hi-Z (bus floats)	0	RD low	0 1 0
	T3	C0H	30H (data in)	0	RD low, rises at end	0 1 0
M3 (memory read, 3T)	T1	C0H	52H	1	-	0 1 0
	T2	C0H	Hi-Z (bus floats)	0	RD low	0 1 0
	T3	C0H	C0H (data in)	0	RD low, rises at end	0 1 0
M4 (memory read, 3T)	T1	C0H	30H	1	-	0 1 0
	T2	C0H	Hi-Z (bus floats)	0	RD low	0 1 0
	T3	C0H	data (data in)	0	RD low, rises at end	0 1 0

The first three cycles are the fetch of the instruction (opcode and operand address); the fourth cycle is the execution (reading the data byte).

✓ Answer checked by Claude Opus 5.5 (high effort)

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