Address decoding for input port at 8050H

LDA 8050H is a memory read instruction, so the port is memory-mapped: the CPU gives IO/M' = 0, the full 16-bit address 8050H and then RD'. The circuit must therefore decode all 16 address lines and IO/M' (no foldback).

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

Address pattern

8050H = 1000 0000 0101 0000
        A15            A6 A4 = 1, all other lines = 0

• Lines that must be 1: A15, A6, A4.
• Lines that must be 0: A14–A7, A5, A3–A0, and IO/M'.

Design using a 74LS138

• Select inputs: C = A6, B = A5, A = A4 → pattern 1 0 1 → output Y5'.
• Enable G1 = A15 (must be 1).
• Enable G2A' = OR of (A14, A13, A12, A11, A10, A9, A8, A7). It is 0 only if all eight lines are 0.
• Enable G2B' = OR of (A3, A2, A1, A0, IO/M'). It is 0 only if these lines are all 0.

 A6 --- C \
 A5 --- B  | 74LS138
 A4 --- A /
 A15 ------------ G1
 A14..A7 -[OR8]-- G2A'
 A3..A0,IO/M' -[OR5]- G2B'
                  Y5' --[OR]-- G' of 74LS244
                           ^   (input port buffer)
                          RD'
 Port data lines -> 74LS244 -> D7..D0 (AD7..AD0)

Working

When the CPU executes LDA 8050H, all conditions are met only for address 8050H, so Y5' becomes low. With RD' low the OR gate enables the 74LS244 buffer; the port data goes on the data bus and the 8085 loads it into the accumulator. For every other address Y5' stays high and the buffer is in high impedance.