- 2073 Bhadra · 2+6 marks
Timing diagram of STA 8050H
Short answer
A bus timing diagram depicts address, data, and control signals per T-state. STA 8050H uses four cycles: opcode fetch, two memory reads to get 50H and 80H forming address, and a memory write to store A at 8050H; total 13 T-states.
Explain bus timing diagram. Draw and explain the timing diagram of the 8085 instruction STA 8050H.
Bus timing diagram
A bus timing diagram shows the state of the address lines, data lines and control signals (ALE, RD, WR, IO/M, S1, S0) against the clock, T-state by T-state, during one machine cycle. It tells exactly when the address is valid, when data is read or written and which device is selected. It is used to design memory/I/O interfaces and to check timing requirements.
Basic pattern of an opcode fetch cycle (4T):
| T1 | T2 | T3 | T4 |
CLK | _|-|_| _|-|_| _|-|_| _|-|_ |
ALE | HIGH| low | low | low |
A15-A8 | PCH (address valid ........|
AD7-0 | PCL | -- |opcode| -- |
RD | high| LOW | LOW | high |
IO/M | low (memory operation) |
STA 8050H
STA 8050H (opcode 32H) stores the accumulator into memory location 8050H. It is a 3-byte instruction with 4 machine cycles: opcode fetch (4T), memory read (3T), memory read (3T), memory write (3T), total 13 T-states. Assume it is stored at 2000H: bytes 32H, 50H, 80H.
| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| M1 (opcode fetch, 4T) | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 | |
| T3 | 20H | 32H (opcode in) | 0 | RD low, rises at end | 0 1 1 | |
| T4 | - | - | 0 | none (decode) | 0 1 1 | |
| M2 (memory read, 3T) | T1 | 20H | 01H | 1 | - | 0 1 0 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 20H | 50H (data in) | 0 | RD low, rises at end | 0 1 0 | |
| M3 (memory read, 3T) | T1 | 20H | 02H | 1 | - | 0 1 0 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 20H | 80H (data in) | 0 | RD low, rises at end | 0 1 0 | |
| M4 (memory write, 3T) | T1 | 80H | 50H | 1 | - | 0 0 1 |
| T2 | 80H | A (data out) | 0 | WR low | 0 0 1 | |
| T3 | 80H | A | 0 | WR low, rises at end | 0 0 1 |
Explanation
- M1 (opcode fetch): PC = 2000H on the bus, ALE high in T1; RD low in T2-T3; opcode 32H is read into IR and decoded in T4.
- M2 (memory read): address 2001H; RD low; low-order address byte 50H goes to register Z.
- M3 (memory read): address 2002H; RD low; high-order address byte 80H goes to register W.
- M4 (memory write): WZ = 8050H is put on the bus (80H on A15-A8, 50H on AD7-AD0 with ALE high in T1). In T2 the CPU places the content of A on AD7-AD0 and WR goes low; the memory stores the data when WR rises at the end of T3. IO/M = 0, S1 = 0, S0 = 1.
✓ Answer checked by Claude Opus 5.5 (high effort)
Related questions
- Timing diagram of STA, program time · Microprocessor, chapter 2
- Bus timing of OUT 42H · Microprocessor, chapter 2
- RIM instruction in 8085 · Microprocessor, chapter 5
- Synchronous/asynchronous bus; LXI timing · Microprocessor, chapter 2 · asked 2×
- Timing diagram of LDA 2080H · Microprocessor, chapter 2 · asked 2×
- Timing diagram of LXI D, 2465H · Microprocessor, chapter 2 · asked 2×
- 8255 mode 2 operation with timing diagram · Instrumentation II, chapter 2
- Instruction cycle state diagram with interrupt · Computer Organization and Architecture, chapter 1 · asked 6×
- Four-segment instruction pipeline and space-time diagram · Computer Organization and Architecture, chapter 4 · asked 5×
- SISO shift register with timing diagram · Digital Logic, chapter 7 · asked 9×