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Synchronous/asynchronous bus; LXI timing
Short answer
A synchronous bus uses a common clock for fixed-timing transfers; an asynchronous bus uses handshaking. LXI B,1234H is a 3-byte instruction taking 10 T-states: opcode fetch (4T), two memory reads (3T each) to load 34H into C and 12H into B from consecutive addresses.
Define synchronous and asynchronous bus. Draw and explain the timing diagram of LXI B, 1234H.
Synchronous bus
In a synchronous bus all data transfers are controlled by a common clock. Transfers start and end at fixed clock edges, and the timing of each operation is known in advance. It is simple and fast but all devices must work at the same speed; slow devices need wait states. The 8085 bus is synchronous (the READY signal can add wait states).
Asynchronous bus
In an asynchronous bus there is no common clock. The transfer uses handshaking signals (e.g., request/acknowledge or Data Valid/Data Accepted), so a sender and a receiver of any speed can communicate. It is more flexible but slower and needs more control logic.
| Point | Synchronous | Asynchronous |
|---|---|---|
| Timing | Common clock | Handshake signals |
| Speed of devices | Same | Any |
| Complexity | Simple | Complex |
Timing diagram of LXI B,1234H
LXI B,1234H loads B = 12H, C = 34H. It is a 3-byte instruction (opcode 01H) with 3 machine cycles: opcode fetch (4T), memory read (3T), memory read (3T) = 10 T-states. Assume it is stored at 2000H, 2001H, 2002H (bytes 01, 34, 12).
| M-cycle | T | A15-A8 | AD7-AD0 | ALE | Control | IO/M S1 S0 |
|---|---|---|---|---|---|---|
| M1 (opcode fetch, 4T) | T1 | 20H | 00H (PCL) | 1 | - | 0 1 1 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 1 | |
| T3 | 20H | 01H (opcode in) | 0 | RD low, rises at end | 0 1 1 | |
| T4 | - | - | 0 | none (decode) | 0 1 1 | |
| M2 (memory read, 3T) | T1 | 20H | 01H | 1 | - | 0 1 0 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 20H | 34H (data in) | 0 | RD low, rises at end | 0 1 0 | |
| M3 (memory read, 3T) | T1 | 20H | 02H | 1 | - | 0 1 0 |
| T2 | 20H | Hi-Z (bus floats) | 0 | RD low | 0 1 0 | |
| T3 | 20H | 12H (data in) | 0 | RD low, rises at end | 0 1 0 |
| M1 (OF) | M2 (MR) | M3 (MR) |
|T1 |T2 |T3 |T4 |T1 |T2 |T3 |T1 |T2 |T3 |
ALE |HI |lo |lo |lo |HI |lo |lo |HI |lo |lo |
RD |hi |LO |LO |hi |hi |LO |LO |hi |LO |LO |
WR |hi |hi |hi |hi |hi |hi |hi |hi |hi |hi |
(HI/hi = high level, LO/lo = low level)
Explanation
- M1: In T1 the address 2000H (PC) is put on the bus: 20H on A15-A8 and 00H on AD7-AD0, with ALE = 1 so an external latch holds the low byte. IO/M = 0, S1 = S0 = 1. In T2 RD goes low and the memory puts the opcode 01H on the data bus; the CPU reads it in T3 and stores it in IR. T4 is used to decode it; PC = 2001H.
- M2: Address 2001H is sent in T1 (ALE = 1). RD is low during T2-T3 and the byte 34H is read into register C. PC = 2002H.
- M3: Address 2002H is sent, RD low, byte 12H is read into register B. PC = 2003H.
Total = 4 + 3 + 3 = 10 T-states.
✓ Answer checked by Claude Opus 5.5 (high effort)
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