Synchronous circuits; asynchronous mod-12 counter

Synchronous sequential circuit

A synchronous sequential circuit is a sequential circuit in which all flip-flops are driven by a common clock, so the state can change only at the active clock edge. Examples: synchronous counters, shift registers, sequence detectors.

Asynchronous mod-12 counter

It counts 0 to 11 (0000 to 1011) and returns to 0 on the 12th clock pulse.

Construction

• 4 negative-edge JK flip-flops ($2^4 = 16 \ge 12$), $J = K = 1$.
• CLK → FF0; $Q_0$ → clock of FF1; $Q_1$ → FF2; $Q_2$ → FF3.
• Count 12 = 1100 is the first state with $Q_3 = Q_2 = 1$. A NAND gate of $Q_3$ and $Q_2$ drives the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q2  ---|      |

Operation

1. FF0 toggles on every falling edge; each later stage toggles when the previous Q falls 1→0, so the count rises 0, 1, 2, …, 11.
2. On the 12th pulse the outputs go from 1011 towards 1100. As soon as $Q_3 = Q_2 = 1$, the NAND output goes low and clears all flip-flops to 0000. State 1100 lasts only a few nanoseconds.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   10  11  0

$Q_3$ is high for counts 8–11, so it is a divide-by-12 output. IC 7492 is a commercial divide-by-12 ripple counter.