Asynchronous mod-12 up counter, positive edge

A mod-12 asynchronous (ripple) up counter counts 0 to 11 (0000 to 1011) and then resets to 0000. Since $2^3 < 12 \le 2^4$, 4 T flip-flops are needed. Each flip-flop has T = 1, so it toggles at every active clock edge it receives.

Clock connections for positive edge triggering

In an up counter, a flip-flop must toggle when the previous output goes 1 to 0. With positive (rising) edge triggered flip-flops, this 1-to-0 change of Q is the same instant as the 0-to-1 change of $\overline{Q}$. So:

• FF0 is clocked by the external CLK.
• FF1 is clocked by $\overline{Q_0}$, FF2 by $\overline{Q_1}$, FF3 by $\overline{Q_2}$.

Reset logic

The count must stop at 11, so the first unwanted state 12 = 1100 is detected. In 1100 only Q3 and Q2 are 1 (and no earlier count 0 to 11 has both Q3 and Q2 = 1), so

$$\overline{CLR} = \overline{Q_3 Q_2}$$

A 2-input NAND gate drives the active-low CLEAR inputs of all flip-flops. As soon as 1100 appears, the NAND output goes 0 and all flip-flops clear to 0000 (state 1100 exists only for a few ns).

Circuit

      T=1          T=1          T=1          T=1
    +------+     +------+     +------+     +------+
CLK>|> FF0 | +-->|> FF1 | +-->|> FF2 | +-->|> FF3 |
    |   Q0'|-+   |   Q1'|-+   |   Q2'|-+   |      |
    | CLR' |     | CLR' |     | CLR' |     | CLR' |
    +------+     +------+     +------+     +------+
 Outputs: Q0 (LSB), Q1, Q2, Q3 (MSB)
 Q3 --+
      +-->[NAND]--> CLR' of all four flip-flops
 Q2 --+

Count sequence

At the 12th clock the counter reaches 1100 for a moment and is immediately cleared to 0000.

Timing diagram

      1   2   3   4   5   6   7   8   9   10  11  12
CLK  _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0   _|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|__
Q1   _____|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|__
Q2   _____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__________________
Q3   _____________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|__

Q0 toggles at every rising edge of CLK; Q1 toggles when Q0 falls; Q2 when Q1 falls; Q3 when Q2 falls. Q3 is high for counts 8 to 11, so Q3 has frequency $f_{CLK}/12$. (In a real ripple counter each change is delayed by one flip-flop delay from the previous stage.)