Ripple counter; asynchronous mod-11 up counter

Ripple counter

A ripple counter is an asynchronous counter in which only the first flip-flop is driven by the external clock and each following flip-flop is clocked by the output of the previous one. The change of state "ripples" through the chain, one flip-flop after another.

Design: asynchronous mod-11 up counter

1. Number of flip-flops: a mod-11 counter needs 11 states (0 to 10). $2^3 = 8 < 11 \le 2^4 = 16$, so 4 flip-flops are needed. JK flip-flops with $J = K = 1$ (toggle) and negative-edge clocks are used.
2. Clocking: CLK → FF0; $Q_0$ → clock of FF1; $Q_1$ → FF2; $Q_2$ → FF3. With falling-edge triggering, using Q as the next clock gives an up count.
3. Reset logic: the counter should go from 10 (1010) back to 0. So it must be cleared as soon as it reaches 11 = 1011. In 1011, $Q_3 = Q_1 = Q_0 = 1$. In the states 0 to 10, these three bits are never all 1, so a 3-input NAND gate of $Q_3, Q_1, Q_0$ drives the active-low CLEAR of all flip-flops.

$$\overline{CLR} = \overline{Q_3\,Q_1\,Q_0}$$

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
Q1  ---| NAND |o--> CLR of all FFs (active low)
Q0  ---|      |

Count table

Operation: each falling clock edge toggles FF0, and each stage toggles when the previous output falls 1→0, so the count increases by one per pulse. On the 11th pulse the state 1011 appears for a moment, the NAND output becomes 0, all flip-flops clear, and the count restarts from 0000.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|_______
Cnt  0    1   2   3   4   5   6   7   8   9   10  0

$Q_3$ is high for counts 8, 9 and 10, so the output frequency at $Q_3$ is $f_{clk}/11$.