Asynchronous mod-12 down counter

Combinational vs sequential logic circuits

Mod-12 asynchronous down counter (negative-edge JK)

Design idea

1. 12 states need 4 flip-flops ($2^4 = 16 \ge 12$). JK flip-flops with $J = K = 1$ toggle on each falling clock edge.
2. Down counting with negative-edge clocks: a stage must toggle when the previous output goes $0 \to 1$, i.e. when its $\overline{Q}$ goes $1 \to 0$. So FF0 gets CLK, and $\overline{Q_0}$, $\overline{Q_1}$, $\overline{Q_2}$ drive the clocks of FF1, FF2, FF3.
3. Truncating to 12 states: a natural 4-bit down counter counts 15, 14, …, 0. We keep the 12 states 1111 (15) down to 0100 (4). When the count falls from 0100 to 0011, the counter is preset at once to 1111.
4. Preset logic: 0011 is the only state reached in which $Q_3 = Q_2 = 0$ (the ripple transients of the other steps never make both 0). An OR gate gives $Q_3 + Q_2 = 0$ only then, and its output drives the active-low PRESET of all four flip-flops:

$$\overline{PR} = Q_3 + Q_2$$

(If the count 11 → 0 is chosen instead, the reset state 1111 must be decoded, but 1111 also appears as a ripple transient when the count goes from 1000 to 0111, which would cause a false load. The 15 → 4 sequence avoids this.)

Circuit diagram

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0'-o FF1 |Q1'-o FF2 |Q2'-o FF3 |Q3
    +-----+     +-----+     +-----+     +-----+
 (count is read from Q3 Q2 Q1 Q0; each FF has an
  active-low PRESET input)

Q3  ---|    |
       | OR |----> PRESET of all FFs (active low)
Q2  ---|    |

Count sequence

Operation: each falling clock edge toggles FF0. When $Q_0$ rises (0→1), $\overline{Q_0}$ falls and FF1 toggles, and so on, so the count decreases by one per pulse. After the 12th pulse the counter tries to enter 0011; the OR output goes low and presets all flip-flops to 1111, starting a new cycle of 12 states.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾
Q2   ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
Q1   ‾‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______|‾‾‾
Q0   ‾‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  15   14  13  12  11  10  9   8   7   6   5   4   15

$Q_3$ completes one cycle every 12 clock pulses ($f_{clk}/12$).