Types of flip-flops; JK flip-flop

Types of flip-flops

1. SR (set-reset) flip-flop
2. D (data/delay) flip-flop
3. JK flip-flop
4. T (toggle) flip-flop

(Each can be level-triggered or edge-triggered, and master-slave versions also exist.)

JK flip-flop

The JK flip-flop removes the invalid state of the SR flip-flop. With J = K = 1, it toggles.

        +-------------------+
 J ---->|                   |----> Q
 CLK -->|>                  |
 K ---->|                   |----> Q'
        +-------------------+

 Logic diagram:
 J  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[  (3-in) ]       ^   |
 Q' ---[      ]          |   |
 K  ---[NAND2]--R1--[NAND4]--+------ Q'
 CLK---[  (3-in) ]
 Q  ---[      ]

Gate 1 has inputs J, CLK and Q'. Gate 2 has inputs K, CLK and Q. Gates 3 and 4 are cross-coupled NAND gates forming the latch (Q' is also fed to gate 3, and Q to gate 4).

Operation and truth table

• CLK = 0: gates 1 and 2 output 1, so the latch holds its state.
• J = 1, K = 0: if Q = 0, gate 1 is enabled (Q' = 1), so S1 = 0 when CLK = 1 and Q becomes 1 (set).
• J = 0, K = 1: if Q = 1, gate 2 is enabled, so R1 = 0 and Q becomes 0 (reset).
• J = K = 1: only the gate whose feedback input is 1 is enabled, so the state flips (toggle).

Characteristic equation: Q(n+1) = J·Q' + K'·Q.

Because of the feedback from Q and Q', J = K = 1 cannot cause an invalid state. A drawback is that if the clock pulse is long, the output keeps toggling (race-around condition). This is avoided by edge triggering or a master-slave arrangement.