JK flip-flop with tables and timing diagram

A J-K flip-flop is a clocked flip-flop with inputs J (set) and K (reset). Unlike the S-R flip-flop, the input J = K = 1 is allowed and makes the output toggle.

Logic diagram

Edge-triggered J-K using NAND gates; CLK* is a narrow pulse made at each rising edge of CLK by an edge detector (CLK ANDed with its delayed complement):

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

      +---------+
 J ---| J     Q |--- Q
 CLK -|>        |
 K ---| K    Q' |--- Q'
      +---------+
 '>' = edge triggered (a bubble 'o>' means
 negative edge triggered)

Operation

• J = K = 0: G1, G2 disabled, latch holds the state.
• J = 0, K = 1: at the edge G2 gives 0 (if Q = 1) and resets: Q = 0.
• J = 1, K = 0: at the edge G1 gives 0 (if Q = 0) and sets: Q = 1.
• J = K = 1: the gate with the 1 feedback fires, the output toggles once per edge.

Characteristic table

Characteristic equation

K-map for Q+ (rows Q, columns JK)
Q\JK   00  01  11  10
 0      0   0   1   1
 1      1   0   0   1
 Groups: J.Q' (row 0, cells 11,10)
         K'.Q (row 1, cells 00,10)

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Excitation table

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__