Edge triggered JK flip-flop with excitation table

An edge-triggered J-K flip-flop changes its output only at the active edge (here the rising edge) of the clock. At that instant J and K decide whether Q is held, reset, set or toggled; at all other times the inputs have no effect.

Circuit

The flip-flop is a clocked J-K circuit (two input-steering NAND gates G1, G2 plus a NAND latch G3, G4) driven by a narrow pulse CLK* produced by an edge detector.

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

Operation

CLK* is high only for a very short time $\Delta t$ (a few ns) after each rising edge, so gates G1 and G2 are enabled only at that instant. Because the pulse is shorter than the propagation delay of the latch, the output changes at most once per edge (no race-around).

1. J = 0, K = 0: G1 and G2 outputs stay 1, the latch keeps its state: $Q_{n+1} = Q_n$.
2. J = 0, K = 1: if Q = 1, G2 (inputs K, CLK*, Q all 1) gives 0 and resets the latch: Q = 0. If Q is already 0, nothing changes.
3. J = 1, K = 0: if Q = 0, then Q' = 1 and G1 gives 0, which sets the latch: Q = 1.
4. J = 1, K = 1: the gate fed by the "active" output fires: if Q = 0, G1 sets it; if Q = 1, G2 resets it. The output toggles.

Truth (characteristic) table

Characteristic equation:

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Excitation table

The excitation table gives the inputs needed for a required transition $Q_n \to Q_{n+1}$ (x = don't care). It is used when designing counters and sequential circuits.

• 0 to 0: J must be 0 (hold or reset both keep 0), so K = x.
• 0 to 1: J must be 1 (set or toggle), K = x.
• 1 to 0: K must be 1 (reset or toggle), J = x.
• 1 to 1: K must be 0 (hold or set), J = x.

Timing diagram (positive edge, Q starts at 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__