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SR flip-flop diagram, excitation table, equation

Short answer

The SR flip-flop consists of NAND gates with clock gating. Excitation table: Q_n to Q_{n+1} transitions define S and R (0→0: S=0,R=X; 0→1: S=1,R=0; 1→0: S=0,R=1; 1→1: S=X,R=0). Characteristic equation: Q_{n+1} = S + R' Q_n, with the constraint SR=0.

Show logic diagram, excitation table and characteristic equation of SR flip-flop.

Logic diagram (clocked SR flip-flop, NAND)

S ---[NAND1]--S'-->[NAND3]---> Q
CLK -[     ]   Q'-->[     ]
CLK -[NAND2]--R'-->[NAND4]---> Q'
R ---[     ]   Q--->[     ]
 (Q fed to NAND4, Q' fed to NAND3)

NAND1 and NAND2 are steering gates enabled by CLK; NAND3 and NAND4 are cross-coupled (each output feeds the other's input). When CLK = 1: S=1S = 1 sets Q to 1, R=1R = 1 resets Q to 0, S=R=0S = R = 0 holds, and S=R=1S = R = 1 is not allowed.

Excitation table

QnQ_nQn+1Q_{n+1}SR
000X
0110
1001
11X0

Characteristic equation

From the characteristic table (S=R=1S = R = 1 taken as don't care):

SRQnQ_nQn+1Q_{n+1}
0000
0011
0100
0110
1001
1011
11XX
        RQn=00 01 11 10
S=0        0   1  0  0
S=1        1   1  X  X
  • The S=1S = 1 row (with X) gives SS; cells 001, 101 give R′QnR'Q_n.
Qn+1=S+R′ Qn,with SR=0Q_{n+1} = S + R'\,Q_n, \qquad \text{with } SR = 0

✓ Answer checked by Claude Opus 5.5 (high effort)

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