JK flip-flop characteristic and excitation tables

A JK flip-flop is a clocked flip-flop with inputs J (like set) and K (like reset). It removes the invalid state of the SR flip-flop: when $J = K = 1$ the output toggles.

Logic diagram

It is an SR flip-flop with $Q$ and $Q'$ fed back to the input NAND gates.

J ---[NAND1]--S'-->[NAND3]---> Q
CLK -[     ]   Q'-->[     ]
Q' --[     ]
K ---[NAND2]--R'-->[NAND4]---> Q'
CLK -[     ]   Q--->[     ]
Q  --[     ]

NAND1 gets J, CLK and $Q'$; NAND2 gets K, CLK and $Q$; NAND3 and NAND4 form the cross-coupled latch.

Operation (clock active)

• $J = 0, K = 0$: both input NANDs give 1, latch holds: no change.
• $J = 0, K = 1$: if $Q = 1$, NAND2 gives 0 and resets: Q = 0.
• $J = 1, K = 0$: if $Q = 0$, NAND1 gives 0 and sets: Q = 1.
• $J = 1, K = 1$: the gate enabled by feedback changes the state: toggle.

Characteristic table

Characteristic equation

        KQn=00 01 11 10
J=0        0   1  0  0
J=1        1   1  0  1

• $J=1, Q_n=0$ (cells 100, 110) gives $JQ_n'$.
• $K=0, Q_n=1$ (cells 001, 101) gives $K'Q_n$.

$$Q_{n+1} = J\,Q_n' + K'\,Q_n$$

Excitation table

Shows the inputs needed for each required transition:

For example, for $0 \to 1$ we may use $J=1, K=0$ (set) or $J=1, K=1$ (toggle), so $K$ is a don't care.

Note: with a level-triggered JK and $J = K = 1$, the output can toggle many times while the clock is high (race-around condition). It is removed by using an edge-triggered or master-slave JK flip-flop.