D flip-flop with excitation table

A D (data/delay) flip-flop has a single input D. At the active clock edge, Q takes the value of D and holds it until the next active edge. It is formed from a clocked S-R flip-flop by feeding D to S and D' to R.

Logic diagram

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

Symbol

      +---------+
 D ---| D     Q |--- Q
 CLK -|>        |
      |      Q' |--- Q'
      +---------+

Operation

1. No active clock: G1 and G2 outputs are 1, so the NAND latch (G3, G4) keeps the old state.
2. D = 1 at the clock: S = 1, R = 0. G1 gives S* = 0, which sets the latch: Q = 1, Q' = 0.
3. D = 0 at the clock: S = 0, R = 1. G2 gives R* = 0, which resets the latch: Q = 0, Q' = 1.
4. The inverter guarantees $S \neq R$, so the invalid S = R = 1 condition of the S-R flip-flop is removed.

Truth (characteristic) table

Characteristic equation: $Q_{n+1} = D$.

Excitation table

To produce a required change $Q \to Q_{n+1}$, D must simply equal the next state:

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
D     ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾

Q follows D only at rising edges, so Q is D delayed by up to one clock period.