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JK flip-flop operation and truth table

Short answer

The JK flip-flop has inputs J, K, clock and outputs Q, Q'. J=0,K=0 holds state; J=0,K=1 resets to 0; J=1,K=0 sets to 1; J=1,K=1 toggles output. Characteristic equation: Q(n+1)=JQ'+K'Q. Race-around with J=K=1 is solved by edge-triggering.

Explain the operation of JK flip-flop with necessary diagrams and characteristic table.

The JK flip-flop is a clocked flip-flop with two inputs J and K and two outputs Q and Q'. It is a refinement of the SR flip-flop in which the input J = K = 1 is allowed and makes the output toggle.

Block symbol

        +---------+
 J ---->|         |----> Q
 CLK -->|>        |
 K ---->|         |----> Q'
        +---------+

Logic diagram (NAND gates)

 J  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[(3-in)]         ^    |
 Q' ---[      ]         |    |
 K  ---[NAND2]--R1--[NAND4]--+------ Q'
 CLK---[(3-in)]
 Q  ---[      ]

NAND1 has inputs J, CLK and Q'. NAND2 has inputs K, CLK and Q. NAND3 and NAND4 form the cross-coupled latch. The feedback from the outputs to the input gates is the key difference from the SR flip-flop.

Operation

  • J = 0, K = 0: no change, Q(n+1) = Q(n).
  • J = 0, K = 1: reset, Q = 0.
  • J = 1, K = 0: set, Q = 1.
  • J = 1, K = 1: toggle, Q(n+1) = Q(n)'.

Characteristic table

JKQ(n)Q(n+1)
0000
0011
0100
0110
1001
1011
1101
1110

Characteristic equation: Q(n+1) = JQ' + K'Q.

With J = K = 1, if the clock pulse is wider than the propagation delay, the output toggles many times (race-around condition). This is removed by edge triggering or by using a master-slave JK flip-flop.

✓ Answer checked by Claude Opus 5.5 (high effort)

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