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SR drawback; edge triggered JK flip-flop

Short answer

The SR flip-flop’s drawback is the forbidden S=R=1 input, leading to race and unpredictable output. The edge-triggered JK flip-flop solves this by using J and K; at the active clock edge, J=K=1 toggles, while other combinations hold, set, or reset, with no invalid state.

Write down the drawback of SR Flip-Flop. Explain the operation of edge triggered JK Flip-Flop with timing diagram and truth table.

Drawback of S-R flip-flop

  • With S = R = 1 (both active) both outputs are forced to the same level, so Q and Q' are no longer complements. This input is forbidden/invalid.
  • When S and R return from 1,1 to 0,0 together, the next state depends on which gate is faster, so the output is unpredictable (race).
  • The designer must always make sure S and R are never both 1, which limits its use. (The J-K flip-flop removes this drawback by toggling for J = K = 1.)

Edge-triggered J-K flip-flop

An edge-triggered J-K flip-flop responds to J and K only at the active (here rising) clock edge. A small edge-detector circuit turns each rising edge into a very narrow pulse CLK* that enables the input gates.

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK
          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

Operation

  • J = K = 0: G1 and G2 are disabled (output 1), the latch holds: no change.
  • J = 0, K = 1: at the edge G2 gives 0 only if Q = 1, so the flip-flop resets (Q = 0).
  • J = 1, K = 0: at the edge G1 gives 0 only if Q' = 1, so the flip-flop sets (Q = 1).
  • J = K = 1: the gate whose feedback input is 1 fires, so the output toggles. Since CLK* is narrower than the propagation delay, it toggles only once per edge (no race-around).

Truth table

CLKJKQ+Action
no edgexxQNo change
edge00QNo change (hold)
edge010Reset
edge101Set
edge11Q'Toggle

Timing diagram (output changes only at rising edges; Q starts at 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__
EdgeJKQ beforeQ afterAction
11001Set
20011Hold
31110Toggle
41101Toggle
50110Reset
61001Set
71110Toggle

✓ Answer checked by Claude Opus 5.5 (high effort)

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