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Positive edge SR flip-flop and its state diagram

Short answer

A positive edge-triggered S-R flip-flop updates only at the rising clock edge. Excitation table: Q_n→Q_{n+1}: 0→0: S=0,R=X; 0→1: S=1,R=0; 1→0: S=0,R=1; 1→1: S=X,R=0. Characteristic equation: Q_{n+1}=S+R'Q_n (SR=0). State diagram: state 0 transitions to 1 on SR=10; state 1 to 0 on SR=01; other valid inputs hold.

Explain the operation of positive edge trigger S-R flip-flop with excitation table. Also derive its characteristic equation and state diagram.

Positive edge-triggered S-R flip-flop

It changes state only at the rising (LOW-to-HIGH) edge of the clock. A pulse-transition detector (CLK ANDed with its delayed inverse) gives a very narrow pulse at each rising edge, which enables the NAND steering gates of an SR latch for a moment. S and R values at other times are ignored. Symbol: triangle at CLK (no bubble).

CLKSRQn+1Q_{n+1}Action
↑00QnQ_nNo change
↑010Reset
↑101Set
↑11?Invalid
0, 1, ↓XXQnQ_nNo change

Excitation table

QnQ_nQn+1Q_{n+1}SR
000X
0110
1001
11X0

Characteristic equation

        RQn=00 01 11 10
S=0        0   1  0  0
S=1        1   1  X  X

S=R=1S = R = 1 is a don't care. Grouping gives SS (bottom row) and R′QnR'Q_n (cells 001, 101):

Qn+1=S+R′ Qn,SR=0Q_{n+1} = S + R'\,Q_n, \qquad SR = 0

State diagram

Two states, Q = 0 and Q = 1; arcs labelled with SR.

   SR=00,01              SR=00,10
    +---+    SR=10        +---+
    |   v  ---------->    |   v
   ( Q=0 )              ( Q=1 )
           <----------
              SR=01
  • In state 0: SR=00SR = 00 or 0101 keeps Q=0Q = 0; SR=10SR = 10 moves to state 1.
  • In state 1: SR=00SR = 00 or 1010 keeps Q=1Q = 1; SR=01SR = 01 moves to state 0.
  • SR=11SR = 11 is not allowed.

✓ Answer checked by Claude Opus 5.5 (high effort)

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