Positive edge JK flip-flop and its drawbacks

A positive edge-triggered J-K flip-flop samples J and K only at the rising (0 to 1) edge of the clock. It is built from a clocked J-K NAND circuit whose clock input is a narrow pulse produced by an edge detector.

Circuit diagram

Edge detector (pulse-transition detector):

 CLK --+---------------->+-----+
       |                 | AND |---> CLK*
       +--->[ NOT ]----->+-----+
            (delay dt)
 CLK* = CLK . CLK'(delayed): a spike of width
 about dt at every rising edge of CLK

The NOT gate delays and inverts CLK. Just after CLK rises, the inverter output is still 1 for its propagation delay $\Delta t$, so the AND gate gives a narrow spike CLK*. After the rising edge, at the falling edge and at all other times, CLK* = 0.

J-K section (NAND gates):

          +------+  S*  +------+
 J -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q
 Q' ------|  G1  |  Q'->|  G3  |
          +------+      +------+
          +------+  R*  +------+
 K -------|      |----->|      |
 CLK* ----| NAND |      | NAND |-----> Q'
 Q  ------|  G2  |  Q-->|  G4  |
          +------+      +------+
 G3 and G4 are cross-coupled (NAND latch).
 Q' is fed back to G1, Q is fed back to G2.

      +---------+
 J ---| J     Q |--- Q
 CLK -|>        |
 K ---| K    Q' |--- Q'
      +---------+
 '>' = edge triggered (a bubble 'o>' means
 negative edge triggered)

Operation

G1 has inputs J, CLK*, Q'; G2 has inputs K, CLK*, Q. G3-G4 form an active-low S'-R' latch.

1. No rising edge (CLK = 0):* G1 = G2 = 1, latch holds: Q unchanged whatever J, K are.
2. J = 0, K = 0: G1 = G2 = 1 even at the edge: no change.
3. J = 0, K = 1: at the edge, G2 = (K·CLK*·Q)' = 0 if Q = 1, so the latch resets (Q = 0). If Q was 0 it stays 0.
4. J = 1, K = 0: at the edge, G1 = (J·CLK*·Q')' = 0 if Q = 0, so the latch sets (Q = 1). If Q was 1 it stays 1.
5. J = 1, K = 1: if Q = 0, G1 fires and sets; if Q = 1, G2 fires and resets. Output toggles. Since CLK* lasts less than the propagation delay of the latch, the new output arrives after CLK* is over, so only one toggle happens per edge.

Truth table

$$Q_{n+1} = J\,\overline{Q_n} + \overline{K}\,Q_n$$

Timing diagram (Q initially 0, changes only at rising edges)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
J     ‾‾‾|___|‾‾‾‾‾‾‾|___|‾‾‾‾‾‾‾|
K     _______|‾‾‾‾‾‾‾‾‾‾‾|___|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|___|‾‾‾|__

Drawbacks of J-K flip-flop

• In a level-triggered J-K flip-flop with J = K = 1, the output toggles many times while the clock is high (race-around condition); edge triggering or master-slave construction is needed to avoid it.
• Edge triggering depends on a very narrow pulse whose width (gate delay) is hard to control; it needs two inputs and more gates than a D flip-flop, so it is not convenient for simple data storage.