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Combinational vs sequential; JK flip-flop

Short answer

Combinational circuits' outputs depend only on present inputs, have no memory (e.g., ader). Sequential circuits' outputs depend on inputs and past state, use memory like flip-flops. The JK flip-flop is a clocked sequential device: J=K=0 hold, 01 reset, 10 set, 11 togle; Q(n+1)=JQ'+K'Q.

What is the difference between combinational and sequential circuit? Discuss JK flip-flop with the help of logic diagram.

Combinational versus sequential circuits

PointCombinational circuitSequential circuit
Output depends onPresent inputs onlyPresent inputs and past outputs (state)
MemoryNoneHas memory (flip-flops)
FeedbackNoYes
ClockNot neededUsually clocked
SpeedFasterSlower
ExamplesAdder, MUX, decoder, encoderFlip-flop, register, counter

JK flip-flop

The JK flip-flop is a clocked bistable circuit with inputs J, K, a clock, and outputs Q and Q'. Unlike an SR flip-flop it has no invalid state: J = K = 1 makes it toggle.

 J  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[(3-in)]         ^    |
 Q' ---[      ]         |    |
 K  ---[NAND2]--R1--[NAND4]--+------ Q'
 CLK---[(3-in)]
 Q  ---[      ]

NAND1 (inputs J, CLK, Q') and NAND2 (inputs K, CLK, Q) are steering gates. NAND3 and NAND4 are a cross-coupled latch. The outputs Q and Q' are fed back to the input gates.

Operation

JKQ(n+1)Action
00Q(n)Hold
010Reset
101Set
11Q(n)'Toggle
  • With CLK = 0, the steering gates output 1 and the latch holds.
  • With CLK = 1, the state changes according to J and K as in the table.
  • Characteristic equation: Q(n+1) = JQ' + K'Q.
  • If CLK stays high longer than the gate delay with J = K = 1, the output toggles repeatedly (race-around). This is solved by edge-triggered or master-slave construction.

Uses: counters (J = K = 1 gives a divide-by-2 stage), registers, frequency dividers.

✓ Answer checked by Claude Opus 5.5 (high effort)

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