Master-slave JK flip-flop

Combinational vs sequential circuit

Master-slave J-K flip-flop

A master-slave J-K flip-flop is two clocked latches in series: the master is enabled by CLK and the slave by the inverted clock CLK'. The final outputs Q and Q' are fed back to the master's input gates. It was designed to remove the race-around condition of the level-triggered J-K flip-flop.

        +---------+   Qm   +---------+
 J -----| MASTER  |------->|  SLAVE  |----> Q
        | SR latch|        | SR latch|
 K -----| (gated) |------->| (gated) |----> Q'
        +---------+   Qm'  +---------+
             ^                  ^
 CLK --------+-----[NOT]--------+
 Master enabled when CLK=1, slave when CLK=0.
 Q' is fed back to the J gate and Q to the
 K gate of the master.

Working principle

1. CLK = 1 (master active, slave disabled): the master reads J, K and the fed-back Q, Q' and sets its outputs Qm, Qm' (J = 1, K = 0 sets Qm; J = 0, K = 1 resets Qm; J = K = 1 makes Qm the complement of Q; J = K = 0 holds). The slave is closed, so Q does not change.
2. CLK goes 1 to 0: the master is disabled and freezes Qm. The slave becomes enabled.
3. CLK = 0 (slave active): the slave copies the master (Q = Qm). Since the master is closed, changing Q cannot affect the master during this time.
4. So the output changes only once per clock pulse, at the falling edge, and Q never feeds back into an active master. Toggling for J = K = 1 happens only once, which removes race-around.

 CLK  __|‾‾‾‾|____|‾‾‾‾|____
 Qm   __|‾‾‾‾‾‾‾‾‾|________   (J = K = 1)
 Q    _______|‾‾‾‾‾‾‾‾‾|____
       master   slave copies at falling edge

A drawback is that J and K must not change while CLK = 1 (the master can "catch" a 1), so the inputs should be stable during the high period.