VHDL COMPONENT; JK flip-flop with PROCESS

Component

A component is a design unit (an entity) that is used as a building block inside another design. It must first be declared and then instantiated.

Component declaration (in the architecture's declarative part or in a package) lists the name and ports of the entity to be used:

component component_name
  port ( port_name : mode type; ... );
end component;

Component instantiation (in the architecture body) places it and connects its ports:

label : component_name port map (formal1 => actual1, formal2 => actual2);

The declaration must match the entity's ports. Components allow hierarchy, reuse and structural description. For example, to use the JK flip-flop below as a component (say, twice in a larger design), declare:

component jkff
  port (clk, rst, j, k : in std_logic; q, qn : out std_logic);
end component;

JK flip-flop using a process

library ieee;
use ieee.std_logic_1164.all;

entity jkff is
  port (
    clk : in  std_logic;
    rst : in  std_logic;       -- asynchronous reset, active high
    j   : in  std_logic;
    k   : in  std_logic;
    q   : out std_logic;
    qn  : out std_logic
  );
end entity jkff;

architecture behavioral of jkff is
  signal q_int : std_logic := '0';      -- internal copy of the state
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q_int <= '0';
    elsif rising_edge(clk) then
      if    j = '0' and k = '0' then q_int <= q_int;       -- hold
      elsif j = '0' and k = '1' then q_int <= '0';         -- reset
      elsif j = '1' and k = '0' then q_int <= '1';         -- set
      else                           q_int <= not q_int;   -- toggle
      end if;
    end if;
  end process;

  q  <= q_int;
  qn <= not q_int;
end architecture behavioral;

Operation on the rising edge of clk: JK = 00 holds Q; 01 resets Q to 0; 10 sets Q to 1; 11 toggles Q. The asynchronous rst clears Q at any time. The code was analysed and simulated with GHDL.