VHDL dataflow/behavioural models; JK flip-flop

Dataflow model

The dataflow model describes a circuit by concurrent signal assignments that show how data flows from inputs to outputs, using Boolean equations or when ... else / with ... select. The order of statements does not matter; each statement is evaluated whenever a signal on its right-hand side changes.

-- dataflow description of a half adder
sum   <= a xor b;
carry <= a and b;

Behavioural model

The behavioural model describes what the circuit does in an algorithmic way, using a process with sequential statements (if, case, loop). It does not say which gates are used. It is the best model for sequential circuits such as flip-flops, counters and state machines.

JK flip-flop using a process

Characteristic table: JK = 00 hold, 01 reset, 10 set, 11 toggle.

library ieee;
use ieee.std_logic_1164.all;

entity jkff is
  port (
    clk : in  std_logic;
    rst : in  std_logic;       -- asynchronous reset, active high
    j   : in  std_logic;
    k   : in  std_logic;
    q   : out std_logic;
    qn  : out std_logic
  );
end entity jkff;

architecture behavioral of jkff is
  signal q_int : std_logic := '0';      -- internal copy of the state
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q_int <= '0';
    elsif rising_edge(clk) then
      if    j = '0' and k = '0' then q_int <= q_int;       -- hold
      elsif j = '0' and k = '1' then q_int <= '0';         -- reset
      elsif j = '1' and k = '0' then q_int <= '1';         -- set
      else                           q_int <= not q_int;   -- toggle
      end if;
    end if;
  end process;

  q  <= q_int;
  qn <= not q_int;
end architecture behavioral;

The process is sensitive to clk and rst. The internal signal q_int is used so that q can be read back for the toggle and for qn. The code was analysed and simulated with GHDL for set, hold, toggle and reset.