VHDL models; full adder structural

Models in VHDL

1. Behavioral model: describes the function algorithmically inside processes (if/case), without describing the gate structure. Example: process (a,b,cin) ... sum <= ....
2. Dataflow model: concurrent signal assignments with Boolean expressions, showing the flow of data: sum <= a xor b xor cin;.
3. Structural model: interconnection of components using port maps, like a netlist; it reflects the real hardware hierarchy.
4. Mixed model: a combination of the above in one architecture.

Full adder from two half adders and an OR gate

        +-------+  s1   +-------+
 a ---->|       |------>|       |----> sum
 b ---->|  HA1  |  cin->|  HA2  |
        +-------+       +-------+
           | c1             | c2
           |   +------+     |
           +-->|  OR  |<----+
               +------+
                  |
                  v
                 cout

HA1 adds a and b, giving s1 and c1; HA2 adds s1 and cin, giving sum and c2; cout = c1 OR c2.

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
  port (a, b : in std_logic; sum, carry : out std_logic);
end entity half_adder;

architecture dataflow of half_adder is
begin
  sum   <= a xor b;
  carry <= a and b;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity or2 is
  port (a, b : in std_logic; y : out std_logic);
end entity or2;

architecture dataflow of or2 is
begin
  y <= a or b;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
  port (
    a, b, cin : in  std_logic;
    sum, cout : out std_logic
  );
end entity full_adder;

architecture structural of full_adder is
  component half_adder
    port (a, b : in std_logic; sum, carry : out std_logic);
  end component;
  component or2
    port (a, b : in std_logic; y : out std_logic);
  end component;

  signal s1, c1, c2 : std_logic;     -- internal wires
begin
  ha1 : half_adder port map (a => a,  b => b,   sum => s1,  carry => c1);
  ha2 : half_adder port map (a => s1, b => cin, sum => sum, carry => c2);
  o1  : or2        port map (a => c1, b => c2,  y => cout);
end architecture structural;

The structural description was analysed and simulated with GHDL for all 8 input combinations (sum = a xor b xor cin, cout = majority of a, b, cin).