Skip to main content

2-bit fast adder; full subtractor from half subtractors

Short answer

A 2-bit fast adder uses carry look-ahead: Gi = AiBi, Pi = Ai⊕Bi; C1 = G0+P0C0, C2 = G1+P1G0+P1P0C0; sums S0 = P0⊕C0, S1 = P1⊕C1. A full subtractor is built with two half subtractors: first gives D1 = A⊕B, B1 = A'B; second gives D = D1⊕Bin, B2 = (A⊕B)'Bin; OR yields Bo = B1+B2.

Define and design 2-bit binary fast adder. Draw the circuit diagram of full subtractor using half subtractor.

2-bit binary fast adder

A fast adder (carry look-ahead adder) is a parallel adder in which all carries are produced directly from the input bits and the input carry, instead of waiting for the carry to ripple through each stage. This makes the addition time almost independent of the number of bits.

For each bit:

Gi=AiBi (carry generate),Pi=Ai⊕Bi (carry propagate)G_i = A_iB_i \ (\text{carry generate}), \qquad P_i = A_i \oplus B_i \ (\text{carry propagate})

Carries for 2 bits (A1A0+B1B0+C0A_1A_0 + B_1B_0 + C_0):

C1=G0+P0C0C2=G1+P1C1=G1+P1G0+P1P0C0\begin{aligned} C_1 &= G_0 + P_0C_0 \\ C_2 &= G_1 + P_1C_1 = G_1 + P_1G_0 + P_1P_0C_0 \end{aligned}

Sums:

S0=P0⊕C0,S1=P1⊕C1S_0 = P_0 \oplus C_0, \qquad S_1 = P_1 \oplus C_1
A0,B0 -[XOR]-P0   -[AND]-G0
A1,B1 -[XOR]-P1   -[AND]-G1

C1 = G0 + P0.C0           (1 AND, 1 OR)
C2 = G1 + P1.G0 + P1.P0.C0 (2 AND, 1 OR)

S0 = P0 xor C0 ; S1 = P1 xor C1  (2 XOR)
C2 is the output carry.

Since C2C_2 comes from a two-level AND–OR circuit, it is ready after the same delay as C1C_1.

Full subtractor using half subtractors

D=A⊕B⊕Bin,Bo=A′B+(A⊕B)′BinD = A \oplus B \oplus B_{in}, \qquad B_o = A'B + (A \oplus B)'B_{in}
  • HS1 (AA, BB): D1=A⊕BD_1 = A \oplus B, B1=A′BB_1 = A'B
  • HS2 (D1D_1, BinB_{in}): D=D1⊕BinD = D_1 \oplus B_{in}, B2=D1′BinB_2 = D_1'B_{in}
  • Bo=B1+B2B_o = B_1 + B_2 (one OR gate)
A --->[ HS1 ]--D1-->[ HS2 ]----------> D
B --->[     ]  Bin->[     ]
         |B1           |B2
         +----->[OR]<--+
                  +------------------> Bo

✓ Answer checked by Claude Opus 5.5 (high effort)

All Digital Logic chapter 5 questions →