2-bit fast adder and its advantage

A fast adder (carry look-ahead adder, CLA) is a parallel adder that produces the carries for all bit positions at the same time, directly from the inputs, instead of letting the carry ripple from stage to stage.

Principle

For bit $i$:

• Carry generate $G_i = A_iB_i$: a carry is produced regardless of $C_i$.
• Carry propagate $P_i = A_i \oplus B_i$: an incoming carry is passed on.

$$C_{i+1} = G_i + P_iC_i, \qquad S_i = P_i \oplus C_i$$

2-bit fast adder

$$\begin{aligned} C_1 &= G_0 + P_0C_0 \\ C_2 &= G_1 + P_1G_0 + P_1P_0C_0 \\ S_0 &= P_0 \oplus C_0 \\ S_1 &= P_1 \oplus C_1 \end{aligned}$$

Logic diagram

A0 B0 --+--[XOR]--> P0
        +--[AND]--> G0
A1 B1 --+--[XOR]--> P1
        +--[AND]--> G1

P0,C0 ----[AND]--+
G0 --------------+--[OR]--> C1

P1,G0 ----[AND]--+
P1,P0,C0 -[AND]--+--[OR]--> C2 (carry out)
G1 --------------+

P0,C0 --[XOR]--> S0
P1,C1 --[XOR]--> S1

Working: the P and G signals appear after one gate delay; $C_1$ and $C_2$ appear after two more gate delays (AND then OR); the sums after one more XOR delay. $C_2$ does not wait for $C_1$.

Example: $A = 11$, $B = 01$, $C_0 = 0$: $G_0 = 1, P_0 = 0, G_1 = 0, P_1 = 1$; $C_1 = 1$, $C_2 = 0 + 1\cdot1 + 0 = 1$; $S_0 = 0$, $S_1 = 1 \oplus 1 = 0$. Result $C_2S_1S_0 = 100 = 4$ (3 + 1). Correct.

Advantages of a fast adder

1. Much higher speed: carry delay is constant (about 3–4 gate delays), not $n$ times one stage delay as in a ripple adder.
2. Delay does not grow with word length within a block, so it suits fast ALUs.
3. Blocks can be cascaded with a second level of look-ahead (IC 74182) for wide adders.
4. Output settles quickly, with fewer glitches.

(Cost: more gates and gates with many inputs, so very wide single-level CLAs are impractical.)