Two 4-bit parallel adder

A 4-bit parallel adder adds two 4-bit binary numbers $A = A_3A_2A_1A_0$ and $B = B_3B_2B_1B_0$ at the same time. It uses four full adders connected in cascade: the carry-out of each full adder is the carry-in of the next higher stage. It is also called a ripple-carry adder (IC 7483 / 74283).

Diagram

  A3 B3      A2 B2      A1 B1      A0 B0
   | |        | |        | |        | |
 +-----+    +-----+    +-----+    +-----+
 | FA3 |<C3-| FA2 |<C2-| FA1 |<C1-| FA0 |<- C0
 +-----+    +-----+    +-----+    +-----+
  |   |        |          |          |
 C4   S3       S2         S1         S0

Each full adder gives

$$S_i = A_i \oplus B_i \oplus C_i, \qquad C_{i+1} = A_iB_i + B_iC_i + A_iC_i$$

Operation

1. All bits of A and B are applied to the full adders at the same time; $C_0$ is normally 0.
2. FA0 adds $A_0$, $B_0$, $C_0$ and gives $S_0$ and $C_1$.
3. $C_1$ goes to FA1, which then gives $S_1$ and $C_2$, and so on.
4. FA3 gives $S_3$ and the final carry $C_4$, which is the fifth bit of the sum.
5. The output $C_4S_3S_2S_1S_0$ is valid only after the carry has passed through all stages.

Example: $A = 0110\ (6)$, $B = 0111\ (7)$:

Result $C_4S_3S_2S_1S_0 = 01101 = 13$.

Cascading two 4-bit adders

Two such 4-bit adders give an 8-bit adder: $C_4$ of the lower adder (bits 0–3) is connected to $C_0$ of the upper adder (bits 4–7).

Limitation: carry propagation delay. In the worst case the carry passes through every stage, so delay $\approx n \times t_{carry}$. A carry look-ahead adder removes this.