4-bit multiplier with parallel adder

A binary multiplier multiplies two numbers by forming partial products with AND gates and adding them with binary parallel adders (BPA), in the same way as long multiplication by hand.

Let $A = A_3A_2A_1A_0$ (multiplicand) and $B = B_3B_2B_1B_0$ (multiplier). The product has $4 + 4 = 8$ bits, $P_7 \dots P_0$.

Partial products

                    A3   A2   A1   A0
                  x B3   B2   B1   B0
 ------------------------------------
                  A3B0 A2B0 A1B0 A0B0
             A3B1 A2B1 A1B1 A0B1
        A3B2 A2B2 A1B2 A0B2
   A3B3 A2B3 A1B3 A0B3
 ------------------------------------
 P7  P6   P5   P4   P3   P2   P1   P0

Each partial-product bit $A_jB_i$ is one 2-input AND gate, so 16 AND gates are needed. Adding the four rows needs three 4-bit parallel adders.

Design

1. Row 0: $A_3B_0\,A_2B_0\,A_1B_0\,A_0B_0$. Its LSB $A_0B_0$ is directly $P_0$.
2. Adder 1: adds row 1 ($A_3B_1 \dots A_0B_1$) to the upper three bits of row 0 ($0, A_3B_0, A_2B_0, A_1B_0$). Its sum LSB is $P_1$; its carry and upper three sum bits go on.
3. Adder 2: adds row 2 ($A_3B_2 \dots A_0B_2$) to (carry of adder 1, upper three sum bits of adder 1). Its sum LSB is $P_2$.
4. Adder 3: adds row 3 ($A_3B_3 \dots A_0B_3$) to (carry of adder 2, upper three sum bits of adder 2). Its four sum bits give $P_6P_5P_4P_3$ and its carry gives $P_7$.

 A x B0 (4 AND) -> [b3 b2 b1 | b0=P0]
                     |
 A x B1 (4 AND) -> [ 4-bit BPA #1 ] -> s0 = P1
                     | carry + s3 s2 s1
 A x B2 (4 AND) -> [ 4-bit BPA #2 ] -> s0 = P2
                     | carry + s3 s2 s1
 A x B3 (4 AND) -> [ 4-bit BPA #3 ] -> s0 = P3
                     |
               Cout=P7, s3 s2 s1 = P6 P5 P4

Each adder's carry-in $C_0 = 0$.

Example: $1101 \times 1011$ (13 × 11)

Product $= 1000\,1111_2 = 143$, and $13 \times 11 = 143$.

Hardware: 16 AND gates and three 4-bit parallel adders (e.g. three IC 7483). In general an $n \times m$-bit multiplier needs $n \cdot m$ AND gates and $(m-1)$ $n$-bit adders.