n-bit full adder block diagram

An n-bit full adder (n-bit parallel adder) adds two n-bit binary numbers $A = A_{n-1}\dots A_1A_0$ and $B = B_{n-1}\dots B_1B_0$ plus an input carry $C_0$. It is made by cascading $n$ one-bit full adders: the carry output of each stage is connected to the carry input of the next higher stage.

Block diagram

 A(n-1)B(n-1)     A2 B2      A1 B1      A0 B0
    |  |          |  |       |  |       |  |
 +--------+    +------+   +------+   +------+
 | FA n-1 |<...| FA2  |<--| FA1  |<--| FA0  |<-C0
 +--------+ C3 +------+ C2+------+ C1+------+
   |    |         |          |          |
  Cn   S(n-1)     S2         S1         S0

One stage (full adder)

$$S_i = A_i \oplus B_i \oplus C_i$$ $$C_{i+1} = A_iB_i + C_i(A_i \oplus B_i)$$

Operation

1. All $2n$ input bits are applied at the same time (parallel inputs). $C_0$ is 0 for plain addition (it is set to 1 for 2's complement subtraction).
2. FA0 adds $A_0$, $B_0$, $C_0$ and gives $S_0$ and $C_1$.
3. $C_1$ enters FA1, which produces $S_1$ and $C_2$; the carry ripples stage by stage to the left.
4. The last stage gives $S_{n-1}$ and the final carry $C_n$. The result is the $(n+1)$-bit number $C_nS_{n-1}\dots S_0$.

Example (n = 4): $A = 1001\ (9)$, $B = 0111\ (7)$, $C_0 = 0$:

Result $= 1\,0000 = 16$.

Timing and expansion

• Each stage must wait for the carry from the previous stage, so the worst-case delay is about $n \cdot t_c$ (where $t_c$ is the carry delay of one full adder). This carry propagation delay grows with $n$.
• Larger adders are built by cascading 4-bit adder ICs (7483/74283): $C_4$ of one IC goes to $C_0$ of the next.
• For high speed, the carry chain is replaced by a carry look-ahead generator, which forms all carries directly from $G_i = A_iB_i$ and $P_i = A_i \oplus B_i$.
• With XOR gates on the B inputs and $C_0 = 1$, the same circuit works as an n-bit subtractor (adder/subtractor).