VHDL PROCESS; full adder with half adders

PROCESS in VHDL

A process is a concurrent statement that contains sequential statements (if, case, loops, signal and variable assignments). It is the basic way of writing behavioural descriptions.

label : process (sensitivity_list)
  -- declarations (variables)
begin
  -- sequential statements
end process;

• It executes once at start-up, then whenever a signal in the sensitivity list changes, and suspends at end process.
• Statements inside run in order; signal assignments take effect at the end of the process (after a delta delay).
• Several processes in one architecture run concurrently.
• A process with a clock edge (rising_edge(clk)) infers flip-flops; one sensitive to all inputs describes combinational logic.

Full adder using two half adders as components

The half adder is written with a process, and the full adder instantiates it twice: sum = (a xor b) xor cin, cout = c1 or c2.

library ieee;
use ieee.std_logic_1164.all;

-- half adder described with a PROCESS
entity half_adder is
  port (
    a, b  : in  std_logic;
    s, c  : out std_logic          -- sum and carry
  );
end entity half_adder;

architecture behavioral of half_adder is
begin
  process (a, b)                   -- runs whenever a or b changes
  begin
    s <= a xor b;
    c <= a and b;
  end process;
end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;

-- full adder built from two half adders (components) and an OR
entity full_adder is
  port (
    x, y, cin : in  std_logic;
    sum, cout : out std_logic
  );
end entity full_adder;

architecture structural of full_adder is
  component half_adder
    port (a, b : in std_logic; s, c : out std_logic);
  end component;

  signal s1, c1, c2 : std_logic;
begin
  u1 : half_adder port map (a => x,  b => y,   s => s1,  c => c1);
  u2 : half_adder port map (a => s1, b => cin, s => sum, c => c2);
  cout <= c1 or c2;                -- OR gate as a concurrent statement
end architecture structural;

The component half_adder is declared in the architecture of full_adder and instantiated as u1 and u2 with port map. The code was analysed and simulated with GHDL for all 8 input combinations.