Full adder using a single 1:4 DEMUX

A 1:4 demultiplexer with its data input tied to logic 1 behaves as a 2-to-4 decoder: with $A, B$ on the select lines, each output $Y_i$ is one minterm of $A$ and $B$. The third input $C_{in}$ is then combined with these outputs using a few gates.

Truth table of the full adder

Expressing S and $C_{out}$ in terms of the DEMUX outputs

With $S_1 = A$, $S_0 = B$ and data input $D = 1$:

$$Y_0 = A'B',\quad Y_1 = A'B,\quad Y_2 = AB',\quad Y_3 = AB$$

From the table, grouping by $AB$:

$$\begin{aligned} S &= (Y_0 + Y_3)C_{in} + (Y_1 + Y_2)C_{in}' \\ &= (Y_1 + Y_2) \oplus C_{in} \\ C_{out} &= Y_3 + (Y_1 + Y_2)\,C_{in} \end{aligned}$$

(Here $Y_1 + Y_2 = A \oplus B$.)

Circuit

        +----------+
  1 --->| D     Y0 |-- (not used)
        |  1:4  Y1 |--+
  A --->| S1    Y2 |--+--[OR]--- P  (= A xor B)
  B --->| S0    Y3 |------------ Y3
        +----------+

  P, Cin  ---[XOR]-------------------- S
  P, Cin  ---[AND]--- P.Cin --+
  Y3 -------------------------+--[OR]-- Cout

Gates needed: one 2-input OR ($P = Y_1 + Y_2$), one XOR ($S = P \oplus C_{in}$), one AND ($P \cdot C_{in}$) and one OR ($C_{out} = Y_3 + P C_{in}$).

Check: for $A=1, B=1, C_{in}=1$: $Y_3 = 1$, $P = 0$, so $S = 0 \oplus 1 = 1$ and $C_{out} = 1$, i.e. $1+1+1 = 11_2$. Correct.