Decoder; 2-to-4 decoder as a full adder

Decoder

A decoder is a combinational circuit that converts an $n$-bit binary input code into $2^n$ output lines, of which exactly one is active for each input combination. Each output is one minterm of the inputs (e.g. 2-to-4, 3-to-8 (74138), BCD-to-decimal decoders).

Full adder using a 2-to-4 decoder

A 2-to-4 decoder has only two inputs, so feed it $A$ and $B$. Its outputs are the minterms of $A, B$:

$$D_0 = A'B',\quad D_1 = A'B,\quad D_2 = AB',\quad D_3 = AB$$

Group the full-adder truth table by $AB$ and write $S$ and $C_{out}$ in terms of $C_{in}$:

Let $P = D_1 + D_2$ ($= A \oplus B$). Then

$$\begin{aligned} S &= (D_0 + D_3)C_{in} + (D_1 + D_2)C_{in}' = P \oplus C_{in} \\ C_{out} &= D_3 + (D_1 + D_2)C_{in} = D_3 + P\,C_{in} \end{aligned}$$

Circuit

          +--------+
  A ----->| 2-to-4 |-- D0 (unused)
  B ----->| decoder|-- D1 --+
          |        |-- D2 --+--[OR]-- P
          |        |-- D3 ------------- D3
          +--------+

  P, Cin ---[XOR]--------------------- S
  P, Cin ---[AND]--- P.Cin ---+
  D3 -------------------------+--[OR]-- Cout

Gates: 2 OR, 1 XOR, 1 AND.

Check

All eight combinations were verified.

Alternative: two 2-to-4 decoders with enable can be joined (using $A$ on the enables) into a 3-to-8 decoder; then $S = \Sigma m(1,2,4,7)$ and $C_{out} = \Sigma m(3,5,6,7)$ are taken with two 4-input OR gates.