VHDL entity, architecture; D flip-flop

Entity

The entity declaration defines the external interface of a design unit: its name, and its ports (name, direction in/out/inout/buffer, and type). It is like the symbol or black box of the circuit.

entity name is
  port ( signal_name : mode type; ... );
end entity name;

Architecture

The architecture body defines what the entity does, using behavioral, dataflow or structural description. It has a declarative part (signals, components, types) and a statement part between begin and end. One entity can have several architectures.

architecture arch_name of entity_name is
  -- declarations (signals, components, constants)
begin
  -- concurrent statements, processes, component instances
end architecture arch_name;

D flip-flop using a process

The flip-flop copies D to Q at the rising edge of the clock; an asynchronous active-high reset clears Q.

library ieee;
use ieee.std_logic_1164.all;

entity dff is
  port (
    clk : in  std_logic;
    rst : in  std_logic;       -- asynchronous reset, active high
    d   : in  std_logic;
    q   : out std_logic
  );
end entity dff;

architecture behavioral of dff is
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q <= '0';                         -- reset overrides the clock
    elsif rising_edge(clk) then
      q <= d;                           -- store D on the rising edge
    end if;
  end process;
end architecture behavioral;

The process is sensitive to clk and rst. When rst = '1' the output is cleared at once; otherwise on rising_edge(clk) the value of d is stored. Between edges q keeps its value, which makes the process infer a flip-flop. The code was checked with GHDL.