VHDL entity declaration; T flip-flops circuit

Entity declaration

An entity is declared with the keyword entity, a name, and a port list giving each port's name, mode (in, out, inout, buffer) and type, closed by end entity:

entity count2 is
  port (
    clock : in  std_logic;
    q0    : out std_logic;
    q1    : out std_logic
  );
end entity count2;

The architecture then defines the contents.

COUNT2 circuit

The figure shows a 2-bit asynchronous counter: BIT_0 is clocked by CLOCK, the inverter output INV_FF0 clocks BIT_1. The T input of each flip-flop is taken as permanently 1, so each toggles on every rising clock edge. It is a structural description with components tff_ck (toggle flip-flop with only the clock input CK and output Q) and inverter.

library ieee;
use ieee.std_logic_1164.all;

-- Basic components (the T input is taken as permanently '1': toggle on every clock edge)
entity tff_ck is
  port (ck : in std_logic; q : out std_logic);
end entity tff_ck;

architecture behavioral of tff_ck is
  signal state : std_logic := '0';
begin
  process (ck)
  begin
    if rising_edge(ck) then
      state <= not state;
    end if;
  end process;
  q <= state;
end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity inverter is
  port (a : in std_logic; y : out std_logic);
end entity inverter;

architecture dataflow of inverter is
begin
  y <= not a;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity count2 is
  port (
    clock : in  std_logic;
    q0    : out std_logic;
    q1    : out std_logic
  );
end entity count2;

architecture structural of count2 is
  component tff_ck
    port (ck : in std_logic; q : out std_logic);
  end component;
  component inverter
    port (a : in std_logic; y : out std_logic);
  end component;

  signal ff0     : std_logic;        -- output of BIT_0
  signal inv_ff0 : std_logic;        -- output of INV
  signal ff1     : std_logic;        -- output of BIT_1
begin
  bit_0 : tff_ck  port map (ck => clock,   q => ff0);
  inv   : inverter port map (a  => ff0,     y => inv_ff0);
  bit_1 : tff_ck  port map (ck => inv_ff0, q => ff1);

  q0 <= ff0;
  q1 <= ff1;
end architecture structural;

Signals ff0, inv_ff0 and ff1 are the internal wires of the figure. Q0 toggles on each rising edge of CLOCK. BIT_1 is clocked by the inverted Q0, i.e. on each falling edge of Q0, so the pair counts 00, 01, 10, 11, 00 ... on successive clock edges (checked with a GHDL simulation; the flip-flops have an initial value 0).