- 2068 Baisakh · 5 marks
Edge triggered JK flip-flop circuit
Short answer
A narrow pulse from an edge detector enables J and K input gates at the rising clock edge. For J=K=1, the output toggles once because the pulse width is less than the feedback delay, preventing race-around. The latch holds state otherwise.
Draw the circuit diagram of edge triggered JK flip flop and explain it.
An edge-triggered J-K flip-flop changes state only at one edge of the clock (rising edge for positive edge triggering). It consists of an edge (pulse-transition) detector and a J-K NAND circuit.
Circuit diagram
CLK --+---------------->+-----+
| | AND |---> CLK*
+--->[ NOT ]----->+-----+
(delay dt)
CLK* = CLK . CLK'(delayed): a spike of width
about dt at every rising edge of CLK
+------+ S* +------+
J -------| |----->| |
CLK* ----| NAND | | NAND |-----> Q
Q' ------| G1 | Q'->| G3 |
+------+ +------+
+------+ R* +------+
K -------| |----->| |
CLK* ----| NAND | | NAND |-----> Q'
Q ------| G2 | Q-->| G4 |
+------+ +------+
G3 and G4 are cross-coupled (NAND latch).
Q' is fed back to G1, Q is fed back to G2.
Explanation
- Edge detector: the inverter delays CLK by its propagation delay . For this short time after a rising edge both AND inputs are 1, so CLK* is a narrow positive spike. This spike enables G1 and G2 only at the edge.
- Input gates: G1 receives J, CLK*, Q'; G2 receives K, CLK*, Q. Their outputs drive the active-low inputs of the G3-G4 latch.
| J | K | At rising edge | Q+ |
|---|---|---|---|
| 0 | 0 | G1 = G2 = 1, latch holds | Q (no change) |
| 0 | 1 | G2 = 0 if Q = 1 | 0 (reset) |
| 1 | 0 | G1 = 0 if Q = 0 | 1 (set) |
| 1 | 1 | G1 fires if Q = 0, G2 if Q = 1 | Q' (toggle) |
Characteristic equation: .
The CLK* pulse ends before the change of Q can travel back to G1/G2, so for J = K = 1 the output toggles only once per clock edge. This removes the race-around problem of the level-triggered J-K flip-flop.
✓ Answer checked by Claude Opus 5.5 (high effort)
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