Edge triggered SR flip-flop

An edge-triggered S-R flip-flop changes state only at the active edge of the clock (rising edge for positive-edge, falling edge for negative-edge). At all other times, changes on S and R have no effect. It is made of a clocked SR latch with a pulse-transition (edge) detector on the clock input.

Circuit

           +-------------+
S -------->| NAND  NAND  |--+-- Q
           | steering    |  |
CLK-[edge]>| gates latch |  |
  detector | NAND  NAND  |--+-- Q'
R -------->|             |
           +-------------+

Edge detector (positive edge):
CLK --+----------[AND]--> narrow pulse
      +-[NOT]----[   ]
       (delay of NOT gives a short spike)

The NOT gate's delay makes $CLK$ and $\overline{CLK}$ both 1 for a few nanoseconds just after the rising edge, so the AND gives a very narrow pulse. Only during this pulse are the steering gates enabled and the latch can change.

Truth table (positive-edge-triggered)

Timing diagram

edge   1     2     3     4     5
CLK  __|‾‾|__|‾‾|__|‾‾|__|‾‾|__|‾‾|__
S    ‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾
R    _____|‾‾‾‾‾‾‾‾‾‾‾|______________
Q    __|‾‾‾‾‾|___________|‾‾‾‾‾‾‾‾‾‾‾

• Edge 1: $S=1, R=0$: Q sets to 1.
• Edge 2: $S=0, R=1$: Q resets to 0.
• Edge 3: $S=0, R=1$: Q stays 0.
• Edge 4: $S=1, R=0$: Q sets to 1.
• Edge 5: $S=1, R=0$: Q stays 1.

Q changes only just after a rising edge, even though S and R change at other times. This sampling at one instant makes edge-triggered flip-flops suitable for synchronous counters and registers. A negative-edge-triggered SR flip-flop works the same way, but on the falling edge (shown by a bubble with the triangle at CLK).