SR drawbacks; D flip-flop operation

Drawbacks of S-R flip-flop

• With S = R = 1 (both active) both outputs are forced to the same level, so Q and Q' are no longer complements. This input is forbidden/invalid.
• When S and R return from 1,1 to 0,0 together, the next state depends on which gate is faster, so the output is unpredictable (race).
• The designer must always make sure S and R are never both 1, which limits its use. (The J-K flip-flop removes this drawback by toggling for J = K = 1.)

Data (D) flip-flop

A D (data or delay) flip-flop has a single data input D. At the active clock edge, the value of D is copied to Q and held until the next active edge: $Q_{n+1} = D$. It is built from a clocked S-R flip-flop by connecting D to S and D' to R through an inverter, which removes the invalid state.

Logic diagram

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

Graphic symbol

      +---------+
 D ---| D     Q |--- Q
 CLK -|>        |
      |      Q' |--- Q'
      +---------+

Operation

1. Clock inactive (no edge / CLK = 0): G1 and G2 outputs are 1, the NAND latch holds the previous state.
2. D = 1 at the clock: S = 1, R = 0. G1 output S* = 0 sets the latch: Q = 1.
3. D = 0 at the clock: S = 0, R = 1. G2 output R* = 0 resets the latch: Q = 0.
4. S and R are always complements, so the forbidden S = R = 1 state never appears.

Because the output follows the input with a delay of one clock, it is also called a delay flip-flop; it is the basic element of registers and memory.

Truth table

Characteristic equation: $Q_{n+1} = D$.

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
D     ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾

At every rising edge Q takes the value D had just before that edge (D sequence 1, 1, 0, 1, 0, 0, 1 gives Q = 1, 1, 0, 1, 0, 0, 1); changes of D between edges are ignored.