SR flip-flop operation

A flip-flop is a bistable circuit with two stable states that can store one bit of data. The clocked SR flip-flop is the basic flip-flop where S (set) and R (reset) inputs act only when the clock pulse (CLK) is high.

Circuit (NAND gates)

 S  ---[NAND1]--S1--[NAND3]--+------ Q
 CLK---[      ]       ^  \   |
                      |   \  |
                      |    \ v
 CLK---[NAND2]--R1--[NAND4]--+------ Q'
 R  ---[      ]

Gates 1 and 2 are steering gates: S1 = (S·CLK)' and R1 = (R·CLK)'. Gates 3 and 4 are a cross-coupled NAND latch: Q = (S1·Q')' and Q' = (R1·Q)' (Q' feeds gate 3 and Q feeds gate 4).

Block symbol:

      +-------+
  S --|       |-- Q
 CLK -|>      |
  R --|       |-- Q'
      +-------+

Operation

• CLK = 0: the steering gates give 1, so the latch holds its previous state.
• CLK = 1 and S = 0, R = 0: no change, Q(n+1) = Q(n).
• S = 0, R = 1: reset, Q = 0.
• S = 1, R = 0: set, Q = 1.
• S = 1, R = 1: both outputs are forced to the same level, and when the clock returns to 0 the final state is unpredictable. So this condition is invalid (forbidden).

Characteristic table

Characteristic equation: Q(n+1) = S + R'Q(n), with the condition S·R = 0.