JK over SR advantages; D flip-flop

Advantages of J-K over S-R flip-flop

• No invalid state: for S = R = 1 the S-R output is undefined, but J = K = 1 makes the J-K flip-flop toggle, a useful defined state.
• Because it can toggle, it can work as a T flip-flop and is the basic element of counters and frequency dividers.
• It is a universal flip-flop: S-R, D and T operations can all be obtained from it.
• Its excitation table has many don't-cares, which gives simpler logic in counter design.

D flip-flop

A D flip-flop has one data input. At each active clock edge, the output Q becomes equal to D and stays so until the next active edge: $Q_{n+1} = D$. It is made from an S-R flip-flop with an inverter between S and R, so S = R = 1 never occurs.

Logic diagram

 D --+------------>+------+  S*  +------+
     |             | NAND |----->| NAND |---> Q
     |   CLK --+-->|  G1  |  Q'->|  G3  |
     |         |   +------+      +------+
     |         |   +------+  R*  +------+
     |         +-->| NAND |----->| NAND |---> Q'
     +--[NOT]----->|  G2  |  Q-->|  G4  |
                   +------+      +------+
 S = D and R = D' : the forbidden S=R=1 never occurs

Symbol

      +---------+
 D ---| D     Q |--- Q
 CLK -|>        |
      |      Q' |--- Q'
      +---------+

Operation

• CLK inactive: G1 = G2 = 1, the latch keeps its previous state.
• D = 1 at the clock: S = 1, R = 0, G1 output goes 0 and sets the latch, Q = 1.
• D = 0 at the clock: S = 0, R = 1, G2 output goes 0 and resets the latch, Q = 0.

Truth table

Timing diagram (positive edge triggered, Q initially 0)

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
D     ‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾‾|
Q     _|‾‾‾‾‾‾‾|___|‾‾‾|_______|‾‾

Q copies D at each rising edge only, so the output is the input delayed by one clock period. D flip-flops are used in registers, latches for data and as delay elements.