Skip to main content

Flip-flop as state machine; SR to JK

Short answer

A flip-flop acts as a single-bit state machine with two states, where next state depends on inputs and present state. To convert SR to JK, add input logic: S = J·Q' and R = K·Q. Connect J AND Q' to S, and K AND Q to R of an SR flip-flop; the invalid S=R=1 is avoided.

How can we use flip-flop as a state machine? Convert SR flip-flop to JK flip-flop.

Flip-flop as a state machine

A state machine is a circuit whose output depends on its present state and inputs, and which moves from one state to the next at each clock. A flip-flop is the simplest state machine:

  • It stores one bit, so it has two states, Q = 0 and Q = 1. The stored value is the present state.
  • At each clock edge, the next state is decided by the inputs and the present state through its characteristic equation (e.g. Qn+1=JQ‾+K‾QQ_{n+1} = J\overline{Q} + \overline{K}Q).
  • Its behaviour can be drawn as a state diagram with two circles and arrows labelled with inputs, exactly like any finite state machine:
              JK = 1x
     +-------------------------+
     |                         v
  +-------+               +-------+
  | Q = 0 |               | Q = 1 |
  +-------+               +-------+
     ^                         |
     +-------------------------+
              JK = x1
 Self-loop on Q=0: JK = 0x (00 or 01)
 Self-loop on Q=1: JK = x0 (00 or 10)
  • With n flip-flops plus next-state logic, a machine with up to 2n2^n states (counter, sequence detector) is built.

Converting S-R flip-flop to J-K flip-flop

S-R excitation table:

QQ+SR
000x
0110
1001
11x0

Conversion table (Q+ from the J-K table, then S, R from the S-R excitation table):

JKQQ+SR
00000x
0011x0
01000x
011001
100110
1011x0
110110
111001

K-maps:

K-map for S
Q\JK   00  01  11  10
 0      0   0   1   1
 1      x   0   0   x

K-map for R
Q\JK   00  01  11  10
 0      x   x   0   0
 1      0   1   1   0
S=J Q‾,R=K QS = J\,\overline{Q}, \qquad R = K\,Q
            +-----+      +---------+
 J -------->|     |      |         |
 Q' ------->| AND |----->| S     Q |---> Q
            +-----+      |         |
            +-----+ CLK->|>  SR    |
 K -------->|     |      |         |
 Q  ------->| AND |----->| R    Q' |---> Q'
            +-----+      +---------+
 (Q and Q' are fed back from the outputs)

For J = K = 1, S = Q' and R = Q, so the circuit toggles and the forbidden S = R = 1 never occurs.

✓ Answer checked by Claude Opus 5.5 (high effort)

All Digital Logic chapter 6 questions →