MOD-6 synchronous counter, negative edge JK

A synchronous MOD-6 counter goes through 6 states, 000 → 001 → 010 → 011 → 100 → 101 → 000, with all flip-flops triggered by the falling edge of a common clock. Three JK flip-flops are needed ($2^3 = 8 \ge 6$). States 110 and 111 are not used (don't cares).

Excitation table

JK excitation: 0→0: J=0, K=X; 0→1: J=1, K=X; 1→0: J=X, K=1; 1→1: J=X, K=0.

K-maps

$J_0 = K_0 = 1$ (Q0 toggles on every clock).

Equations

$$\begin{aligned} &J_2 = Q_1Q_0,\quad K_2 = Q_0 \\ &J_1 = \overline{Q_2}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}$$

Circuit (negative-edge triggered)

   +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
K0>|K    |    K1>|K    |    K2>|K    |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
J0 = K0 = 1
J1 = Q2'.Q0    K1 = Q0
J2 = Q1.Q0     K2 = Q0

"o" at the clock input shows negative-edge triggering. Only two 2-input AND gates are needed.

Check

Unused states go 110 → 111 → 000, so the counter starts correctly from any power-on state.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾|_______
Q1   ________|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   0   1

All outputs change at the falling clock edges; $Q_2$ gives $f_{clk}/6$.