- Asked 4/22
- 2081 Bhadra · 7 marks
- 2080 Bhadra · 7 marks
- 2076 Asoj
Mod-5 synchronous counter using JK
Short answer
Use three JK flip-flops. J2 = Q1 Q0, K2 = 1; J1 = Q0, K1 = Q0; J0 = Q2', K0 = 1. The counter runs through states 000 to 100 and is self-starting.
Design a mod-5 synchronous counter using positive edge-triggered JK flip flops.
A mod-5 synchronous counter counts 0, 1, 2, 3, 4 and returns to 0 (5 states). Since , 3 flip-flops (Q2 Q1 Q0, Q2 = MSB) are needed. All flip-flops get the same clock (positive edge triggered J-K), and the J, K inputs are found from the excitation table.
Step 1: state diagram
000 -> 001 -> 010 -> 011 -> 100
^ |
+----------------------------+
Unused: 101, 110, 111 (don't cares)
Step 2: J-K excitation table
| Q | Q+ | J | K |
|---|---|---|---|
| 0 | 0 | 0 | x |
| 0 | 1 | 1 | x |
| 1 | 0 | x | 1 |
| 1 | 1 | x | 0 |
Step 3: state table with flip-flop inputs
| State | Q2 | Q1 | Q0 | Q2+ | Q1+ | Q0+ | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | x | 0 | x | 1 | x |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | x | 1 | x | x | 1 |
| 2 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | x | x | 0 | 1 | x |
| 3 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | x | x | 1 | x | 1 |
| 4 | 1 | 0 | 0 | 0 | 0 | 0 | x | 1 | 0 | x | 0 | x |
States 5, 6 and 7 never occur, so all their inputs are don't cares (x).
Step 4: K-maps and simplified expressions
K-map for J2
Q2\Q1Q0 00 01 11 10
0 0 0 1 0
1 x x x x
K-map for K2
Q2\Q1Q0 00 01 11 10
0 x x x x
1 1 x x x
K-map for J1
Q2\Q1Q0 00 01 11 10
0 0 1 x x
1 0 x x x
K-map for K1
Q2\Q1Q0 00 01 11 10
0 x x 1 0
1 x x x x
K-map for J0
Q2\Q1Q0 00 01 11 10
0 1 x x 1
1 0 x x x
K-map for K0
Q2\Q1Q0 00 01 11 10
0 x 1 1 x
1 x x x x
Step 5: logic diagram
+--------+ +--------+ +--------+
J0->|J0 Q0 |J1->|J1 Q1 |J2->|J2 Q2 |
K0->|K0 Q0' |K1->|K1 Q1' |K2->|K2 Q2' |
|> FF0 | |> FF1 | |> FF2 |
+--------+ +--------+ +--------+
CLK ---^-------------^-------------^
Input connections:
J0 <- Q2' K0 <- 1 (HIGH)
J1 <- Q0 K1 <- Q0
J2 <- AND(Q1, Q0) K2 <- 1 (HIGH)
Timing diagram
1 2 3 4 5 6 7
CLK _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0 _|‾‾‾|___|‾‾‾|_______|‾‾‾|__
Q1 _____|‾‾‾‾‾‾‾|___________|‾‾
Q2 _____________|‾‾‾|__________
The counter goes 000, 001, 010, 011, 100, 000, ...; Q2 is high for one clock in five, so the output frequency is .
Unused states check: with these equations, 101 goes to 010, 110 goes to 010 and 111 goes to 000, so the counter returns to the main sequence by itself (self-starting).
✓ Answer checked by Claude Opus 5.5 (high effort)
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