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Mod-5 synchronous counter using JK

Short answer

Use three JK flip-flops. J2 = Q1 Q0, K2 = 1; J1 = Q0, K1 = Q0; J0 = Q2', K0 = 1. The counter runs through states 000 to 100 and is self-starting.

Design a mod-5 synchronous counter using positive edge-triggered JK flip flops.

A mod-5 synchronous counter counts 0, 1, 2, 3, 4 and returns to 0 (5 states). Since 22<5≤232^2 < 5 \le 2^3, 3 flip-flops (Q2 Q1 Q0, Q2 = MSB) are needed. All flip-flops get the same clock (positive edge triggered J-K), and the J, K inputs are found from the excitation table.

Step 1: state diagram

 000 -> 001 -> 010 -> 011 -> 100
  ^                            |
  +----------------------------+
 Unused: 101, 110, 111 (don't cares)

Step 2: J-K excitation table

QQ+JK
000x
011x
10x1
11x0

Step 3: state table with flip-flop inputs

StateQ2Q1Q0Q2+Q1+Q0+J2K2J1K1J0K0
00000010x0x1x
10010100x1xx1
20100110xx01x
30111001xx1x1
4100000x10x0x

States 5, 6 and 7 never occur, so all their inputs are don't cares (x).

Step 4: K-maps and simplified expressions

K-map for J2
Q2\Q1Q0  00  01  11  10
  0       0   0   1   0
  1       x   x   x   x

K-map for K2
Q2\Q1Q0  00  01  11  10
  0       x   x   x   x
  1       1   x   x   x

K-map for J1
Q2\Q1Q0  00  01  11  10
  0       0   1   x   x
  1       0   x   x   x

K-map for K1
Q2\Q1Q0  00  01  11  10
  0       x   x   1   0
  1       x   x   x   x

K-map for J0
Q2\Q1Q0  00  01  11  10
  0       1   x   x   1
  1       0   x   x   x

K-map for K0
Q2\Q1Q0  00  01  11  10
  0       x   1   1   x
  1       x   x   x   x
J2=Q1Q0,K2=1J1=Q0,K1=Q0J0=Q2‾,K0=1\begin{aligned} J_2 &= Q_1 Q_0, & K_2 &= 1 \\ J_1 &= Q_0, & K_1 &= Q_0 \\ J_0 &= \overline{Q_2}, & K_0 &= 1 \end{aligned}

Step 5: logic diagram

     +--------+    +--------+    +--------+
 J0->|J0   Q0 |J1->|J1   Q1 |J2->|J2   Q2 |
 K0->|K0  Q0' |K1->|K1  Q1' |K2->|K2  Q2' |
     |>  FF0  |    |>  FF1  |    |>  FF2  |
     +--------+    +--------+    +--------+
 CLK ---^-------------^-------------^
 Input connections:
   J0 <- Q2'            K0 <- 1 (HIGH)
   J1 <- Q0             K1 <- Q0
   J2 <- AND(Q1, Q0)    K2 <- 1 (HIGH)

Timing diagram

       1   2   3   4   5   6   7
CLK   _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|
Q0    _|‾‾‾|___|‾‾‾|_______|‾‾‾|__
Q1    _____|‾‾‾‾‾‾‾|___________|‾‾
Q2    _____________|‾‾‾|__________

The counter goes 000, 001, 010, 011, 100, 000, ...; Q2 is high for one clock in five, so the output frequency is fCLK/5f_{CLK}/5.

Unused states check: with these equations, 101 goes to 010, 110 goes to 010 and 111 goes to 000, so the counter returns to the main sequence by itself (self-starting).

✓ Answer checked by Claude Opus 5.5 (high effort)

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