Mod-10 negative edge ripple counter with JK

Sequential logic circuit

A sequential logic circuit is a circuit whose output depends on the present inputs and on the past history (stored state) of the circuit. It contains memory elements (flip-flops or latches) and a feedback path; flip-flops, registers and counters are examples.

Mod-10 negative-edge ripple counter

A mod-10 (decade) ripple counter has 10 states, 0000 to 1001. Since $2^3 < 10 \le 2^4$, four JK flip-flops are used.

Connections

• All J and K inputs are tied to logic 1, so every flip-flop toggles on its active (falling) clock edge.
• The external clock goes to FF0 only. $Q_0$ is the clock of FF1, $Q_1$ of FF2 and $Q_2$ of FF3 (negative-edge triggering means a stage toggles when the previous Q falls from 1 to 0, which gives up counting).
• Count 10 = 1010 must not be held. It is the first state with $Q_3 = Q_1 = 1$, so $\overline{Q_3Q_1}$ (NAND) is fed to the active-low CLEAR of all flip-flops.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Operation

1. Initially all flip-flops are cleared: $Q_3Q_2Q_1Q_0 = 0000$.
2. Every falling clock edge toggles FF0. Whenever $Q_0$ goes 1→0, FF1 toggles; whenever $Q_1$ goes 1→0, FF2 toggles; whenever $Q_2$ goes 1→0, FF3 toggles. The count rises 0, 1, 2, …, 9.
3. On the 10th falling edge the outputs try to become 1010. At once the NAND output goes low and clears all flip-flops, so the counter returns to 0000. The false state 1010 exists only for a few nanoseconds.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

Each output changes on the falling edge of the signal that clocks it. $Q_3$ is high only for counts 8 and 9, and its frequency is $f_{clk}/10$. In a real circuit each stage adds a propagation delay $t_{pd}$, so the outputs ripple and a narrow spike appears on $Q_1$ at the reset.