Ripple counter; mod-10 ripple counter

Ripple counter

A ripple counter (asynchronous counter) is a counter in which only the first flip-flop receives the external clock, and the output of each flip-flop acts as the clock of the next one. The change of state ripples through the stages one after another.

Mod-10 ripple counter

Construction

• 10 states (0–9) need 4 flip-flops, since $2^3 < 10 \le 2^4$.
• Four negative-edge JK flip-flops with $J = K = 1$ (toggle mode). CLK → FF0, $Q_0$ → FF1, $Q_1$ → FF2, $Q_2$ → FF3.
• At count 10 (1010), $Q_3$ and $Q_1$ are both 1 for the first time. A NAND gate of $Q_3$ and $Q_1$ drives the active-low CLEAR of all flip-flops, so the counter returns to 0000.

     J=K=1       J=K=1       J=K=1       J=K=1
    +-----+     +-----+     +-----+     +-----+
CLK-o FF0 |Q0--o FF1 |Q1--o FF2 |Q2--o FF3 |Q3
    +--o--+     +--o--+     +--o--+     +--o--+
      CLR         CLR         CLR         CLR

Q3  ---|      |
       | NAND |o--> CLR of all FFs (active low)
Q1  ---|      |

Operation

1. Clear all flip-flops: 0000.
2. Each falling edge of CLK toggles FF0. FF1 toggles every time $Q_0$ falls 1→0; FF2 every time $Q_1$ falls; FF3 every time $Q_2$ falls. The outputs therefore count up in binary.
3. After the 9th pulse the count is 1001. The 10th pulse makes $Q_0$ fall, which toggles $Q_1$ to 1, giving 1010 for a moment. The NAND output becomes 0 and clears all flip-flops to 0000. The next cycle begins.

Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|___
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   8   9   0

• $Q_0$ changes at every falling clock edge ($f/2$).
• $Q_1$, $Q_2$, $Q_3$ change at the falling edges of $Q_0$, $Q_1$, $Q_2$.
• $Q_3$ is high during counts 8 and 9 and gives $f_{clk}/10$.
• In the real circuit each stage adds one propagation delay and a narrow spike appears on $Q_1$ at the 10th pulse (state 1010 before reset).