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- 2079 Baisakh · 2+6 marks
Sync vs async; MOD-10 synchronous counter
Short answer
Synchronous counters have all flip-flops clocked together; asynchronous counters ripple clock from previous stage. MOD-10 synchronous counter uses 4 JK flip-flops: J3=Q2Q1Q0, K3=Q0; J2=K2=Q1Q0; J1=Q3'Q0, K1=Q0; J0=K0=1, counting 0-9 then return to 0.
Define Synchronous and Asynchronous counter. Design a MOD-10 synchronous counter and draw its timing diagram.
Definitions
- Synchronous counter: a counter in which all flip-flops are driven by the same clock pulse, so all outputs change at the same time. Logic gates decide which flip-flops toggle.
- Asynchronous (ripple) counter: a counter in which only the first flip-flop gets the external clock; each later flip-flop is clocked by the output of the previous one, so the outputs change one after another.
Design of MOD-10 synchronous counter (JK flip-flops)
Step 1: 10 states (0000–1001) need 4 JK flip-flops (). States 1010–1111 are don't cares.
Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)
| Present Q3Q2Q1Q0 | Next Q3Q2Q1Q0 | J3 | K3 | J2 | K2 | J1 | K1 | J0 | K0 |
|---|---|---|---|---|---|---|---|---|---|
| 0000 | 0001 | 0 | X | 0 | X | 0 | X | 1 | X |
| 0001 | 0010 | 0 | X | 0 | X | 1 | X | X | 1 |
| 0010 | 0011 | 0 | X | 0 | X | X | 0 | 1 | X |
| 0011 | 0100 | 0 | X | 1 | X | X | 1 | X | 1 |
| 0100 | 0101 | 0 | X | X | 0 | 0 | X | 1 | X |
| 0101 | 0110 | 0 | X | X | 0 | 1 | X | X | 1 |
| 0110 | 0111 | 0 | X | X | 0 | X | 0 | 1 | X |
| 0111 | 1000 | 1 | X | X | 1 | X | 1 | X | 1 |
| 1000 | 1001 | X | 0 | 0 | X | 0 | X | 1 | X |
| 1001 | 0000 | X | 1 | 0 | X | 0 | X | X | 1 |
Step 3: K-maps (only the non-trivial ones)
| J1: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 1 | X | X |
| 01 | 0 | 1 | X | X |
| 11 | X | X | X | X |
| 10 | 0 | 0 | X | X |
| J3: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0 | 0 | 0 | 0 |
| 01 | 0 | 0 | 1 | 0 |
| 11 | X | X | X | X |
| 10 | X | X | X | X |
| K3: Q3Q2 / Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | X | X | X | X |
| 01 | X | X | X | X |
| 11 | X | X | X | X |
| 10 | 0 | 1 | X | X |
and are read the same way.
Step 4: Equations
Step 5: Circuit diagram
+-----+ +-----+ +-----+ +-----+
J0>|J Q|-Q0 J1>|J Q|-Q1 J2>|J Q|-Q2 J3>|J Q|-Q3
| FF0 | | FF1 | | FF2 | | FF3 |
K0>|K | K1>|K | K2>|K | K3>|K |
+--o--+ +--o--+ +--o--+ +--o--+
| | | |
CLK---+-------------+-------------+-------------+
J0 = K0 = 1 J1 = Q3'.Q0 K1 = Q0
J2 = K2 = Q1.Q0 J3 = Q2.Q1.Q0 K3 = Q0
Step 6: Timing diagram
CLK __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3 ________________________________|‾‾‾‾‾‾‾|_______
Q2 ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1 ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0 ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt 0 1 2 3 4 5 6 7 8 9 0 1
All flip-flops change together on the falling clock edge. is high for counts 8 and 9, giving . The unused states return to the main count within two clocks (1010→1011→0100, 1100→1101→0100, 1110→1111→0000), so the counter is self-starting.
✓ Answer checked by Claude Opus 5.5 (high effort)
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