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Sync vs async; MOD-10 synchronous counter

Short answer

Synchronous counters have all flip-flops clocked together; asynchronous counters ripple clock from previous stage. MOD-10 synchronous counter uses 4 JK flip-flops: J3=Q2Q1Q0, K3=Q0; J2=K2=Q1Q0; J1=Q3'Q0, K1=Q0; J0=K0=1, counting 0-9 then return to 0.

Define Synchronous and Asynchronous counter. Design a MOD-10 synchronous counter and draw its timing diagram.

Definitions

  • Synchronous counter: a counter in which all flip-flops are driven by the same clock pulse, so all outputs change at the same time. Logic gates decide which flip-flops toggle.
  • Asynchronous (ripple) counter: a counter in which only the first flip-flop gets the external clock; each later flip-flop is clocked by the output of the previous one, so the outputs change one after another.

Design of MOD-10 synchronous counter (JK flip-flops)

Step 1: 10 states (0000–1001) need 4 JK flip-flops (Q3Q2Q1Q0Q_3Q_2Q_1Q_0). States 1010–1111 are don't cares.

Step 2: Excitation table (JK: 0→0: 0X, 0→1: 1X, 1→0: X1, 1→1: X0)

Present Q3Q2Q1Q0Next Q3Q2Q1Q0J3K3J2K2J1K1J0K0
000000010X0X0X1X
000100100X0X1XX1
001000110X0XX01X
001101000X1XX1X1
010001010XX00X1X
010101100XX01XX1
011001110XX0X01X
011110001XX1X1X1
10001001X00X0X1X
10010000X10X0XX1

Step 3: K-maps (only the non-trivial ones)

J1: Q3Q2 / Q1Q000011110
0001XX
0101XX
11XXXX
1000XX
J3: Q3Q2 / Q1Q000011110
000000
010010
11XXXX
10XXXX
K3: Q3Q2 / Q1Q000011110
00XXXX
01XXXX
11XXXX
1001XX

K1=Q0K_1 = Q_0 and J2=K2=Q1Q0J_2 = K_2 = Q_1Q_0 are read the same way.

Step 4: Equations

J3=Q2Q1Q0,K3=Q0J2=Q1Q0,K2=Q1Q0J1=Q3‾Q0,K1=Q0J0=1,K0=1\begin{aligned} &J_3 = Q_2Q_1Q_0,\quad K_3 = Q_0 \\ &J_2 = Q_1Q_0,\quad K_2 = Q_1Q_0 \\ &J_1 = \overline{Q_3}Q_0,\quad K_1 = Q_0 \\ &J_0 = 1,\quad K_0 = 1 \end{aligned}

Step 5: Circuit diagram

   +-----+       +-----+       +-----+       +-----+
J0>|J   Q|-Q0 J1>|J   Q|-Q1 J2>|J   Q|-Q2 J3>|J   Q|-Q3
   | FF0 |       | FF1 |       | FF2 |       | FF3 |
K0>|K    |    K1>|K    |    K2>|K    |    K3>|K    |
   +--o--+       +--o--+       +--o--+       +--o--+
      |             |             |             |
CLK---+-------------+-------------+-------------+
J0 = K0 = 1        J1 = Q3'.Q0   K1 = Q0
J2 = K2 = Q1.Q0    J3 = Q2.Q1.Q0  K3 = Q0

Step 6: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q3   ________________________________|‾‾‾‾‾‾‾|_______
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______________
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_______________
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾
Cnt  0    1   2   3   4   5   6   7   8   9   0   1

All flip-flops change together on the falling clock edge. Q3Q_3 is high for counts 8 and 9, giving fQ3=fclk/10f_{Q_3} = f_{clk}/10. The unused states return to the main count within two clocks (1010→1011→0100, 1100→1101→0100, 1110→1111→0000), so the counter is self-starting.

✓ Answer checked by Claude Opus 5.5 (high effort)

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