Sync vs async; 3-bit synchronous up counter (T)

Synchronous vs asynchronous counter

Design of 3-bit synchronous up counter (T flip-flops)

Step 1: Count 000 → 001 → … → 111 → 000. Three T flip-flops ($Q_2Q_1Q_0$) share the clock. A T flip-flop toggles when $T = 1$, so $T = Q \oplus Q^+$.

Step 2: Excitation table

Step 3: K-maps

$T_0 = 1$ in every row.

Step 4: Equations

$$\begin{aligned} &T_2 = Q_1Q_0 \\ &T_1 = Q_0 \\ &T_0 = 1 \end{aligned}$$

A stage toggles only when all lower bits are 1 (the carry condition).

Step 5: Circuit diagram

   +-----+       +-----+       +-----+
T0>|T   Q|-Q0 T1>|T   Q|-Q1 T2>|T   Q|-Q2
   | FF0 |       | FF1 |       | FF2 |
   |     |       |     |       |     |
   +--o--+       +--o--+       +--o--+
      |             |             |
CLK---+-------------+-------------+
T0 = 1    T1 = Q0    T2 = Q1.Q0 (one AND gate)

Step 6: Timing diagram

CLK  __|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾
Q2   ________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___
Q1   ________|‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|___
Q0   ____|‾‾‾|___|‾‾‾|___|‾‾‾|___|‾‾‾|___
Cnt  0    1   2   3   4   5   6   7   0

All outputs change together at the falling clock edge; $Q_0$, $Q_1$, $Q_2$ have frequencies $f/2$, $f/4$, $f/8$.